EMERSON PACSystems VersaMax MICRO PLC & NANO PLC. USER MANUAL (2019)

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22.4.3

%S References

References in %S memory are read only.

Reference

Nickname Definition

%S0001

FST_SCN

Set to 1 when the current sweep is the first sweep.

%S0002

LST_SCN

Reset from 1 to 0 when the current sweep is the last sweep.

%S0003

T_10MS

0.01 second timer contact.

%S0004

T_100MS

0.1 second timer contact.

%S0005

T_SEC

1.0 second timer contact.

%S0006

T_MIN

1.0-minute timer contact.

%S0007

ALW_ON

Always ON.

%S0008

ALW_OFF

Always OFF.

%S0009

SY_FULL

Set when the PLC fault table fills up. Cleared when an entry is
removed and when the PLC fault table is cleared.

%S0010

IO_FULL

Set when the I/O fault table fills up. Cleared when an entry is
removed from the I/O fault table and when the I/O fault table is
cleared.

%S0011

OVR_PRE

Set when an override exists in %I, %Q, %M, or %G memory.

%S0012

reserved

%S0013

PRG_CHK

Set when background program check is active. Cleared when the
background program check is inactive.

%S0014

PLC_BAT

Set to indicate a bad battery in the CPU. The contact reference is
updated once per sweep. This bit is supported by 28-point Micro
PLCs only.

%S0015, 16

reserved

%S0017

SNPXACT

SNP-X host is actively attached to CPU port 1. (Port 2 defaults to
disabled and must be activated with a CRQ).

%S0018

SNPX_RD

SNP-X host has read data from CPU port 1.

%S0019

SNPX_WT

SNP-X host has written data to CPU port 1.

%S0020

Set ON when a relational function using REAL data executes
successfully. It is cleared when either input is NaN (Not a Number).

%S0021

FF_OVR

Set to report a Fatal Fault Override.

%S0022

USR_SW

Set to reflect the state of the CPU mode switch.

1 = Run/On

0 = Stop/Off

%S0023-32

reserved

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22.4.4

%SA, %SB, and %SC References

References in %SA, %SB, and %SC memory can be both read and written to.

Reference

Nickname Definition

%SA0001

PB_SUM

Set when a checksum calculated on the application program does not
match the reference checksum.  If the fault was due to a temporary
failure, the discrete bit can be cleared by again storing the program
to the Micro PLC.  If the fault was due to a hard RAM failure, the Micro
PLC must be replaced.

%SA0002

OV_SWP

Set when a Micro PLC in CONSTANT SWEEP mode  detects that the
previous sweep took longer  than the  time  specified. Cleared when
the  PLC  detects  that  the  previous  sweep  did  not  take  longer  than
specified. Also cleared during transition from STOP to RUN mode.

%SA0003

APL_FLT

Set when an application fault occurs. Cleared when the Micro PLC
transitions from STOP to RUN mode.

%SA0004-8

reserved

%SA0009

CFG_MM

Set when a configuration mismatch is detected during power-up or a
configuration store. Cleared by powering up the Micro PLC after
correcting the condition.

%SA0010

HRD_CPU

Set when the diagnostics detects a problem with the Micro PLC TOD
clock.
This bit is not supported by Nano and 14-point Micro PLCs.

%SA0011

LOW_BAT

Set when a low battery fault occurs. Cleared by replacing the battery
then powering up the Micro PLC.
This bit is not supported by Nano and 14-point Micro PLCs.

%SA0012,13

reserved

%SA0014

LOS_IOM

Set when an expansion module stops communicating with the CPU.
Cleared by replacing the module and cycling system power.

%SA0015-18

reserved

%SA0019

ADD_IOM

Set when an expansion module is added. Cleared by cycling PLC
power and when the configuration matches the hardware after a
store.

%SA0020-31

reserved

%SB0001-8

reserved

%SB0009

NO_PROG

Set when an attempt is made to put the PLC in Run mode when there
is no executable application program stored in the CPU. Cleared by
storing an application program to the CPU and putting the PLC in Run
mode.

%SB0010

BAD_RAM

Set when the Micro PLC detects corrupted RAM memory at power-
up. Cleared when RAM memory is valid at power-up.

%SB0011

BAD_PWD

Set when a password access violation occurs. Cleared when the PLC
fault table is cleared.

%SB0012

reserved

%SB0013

SFT_CPU

Set when the Micro PLC detects an unrecoverable error in the
software. Cleared by clearing the PLC fault table.

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Reference

Nickname Definition

%SB0014

STOR_ER

Set when an error occurs during a programmer store operation.
Cleared when a store operation is completed successfully.

%SC0001-8

reserved

%SC0009

ANY_FLT

Set when any fault occurs. Cleared when both fault tables are cleared.

%SC0010

SY_FLT

Set when any fault occurs that causes an entry to be placed in the PLC
fault table. Cleared when the PLC fault table is cleared.

%SC0011

IO_FLT

Set when any fault occurs that causes an entry to be placed in the I/O
fault table. Cleared when the I/O fault table is cleared.

%SC0012

SY_PRES

Set as long as there is at least one entry in the PLC fault table. Cleared
when the PLC fault table has no entries.

%SC0013

IO_PRES

Set as long as there is at least one entry in the I/O fault table. Cleared
when the I/O fault table has no entries.

%SC0014

HRD_FLT

Set when a hardware fault occurs. Cleared when both fault tables
have no entries.
This bit is not supported by Nano and 14-point Micro PLCs.

%SC0015

SFT_FLT

Set when a software fault occurs. Cleared when both fault tables have
no entries.

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22.5

How Program Functions Handle Numerical
Data

Regardless of where data is stored in memory

—

in one of the bit memories or one of the

word memories

—

the application program can handle it as different data types.

Type

Name

Description

Data Format

BIT

Bit

A Bit data type is the smallest unit of memory. It
has two states, 1 or 0.

BYTE

Byte

A Byte data type has an 8-bit value. The valid
range is 0 to 255 (0 to FF in hexadecimal).

WORD

A Word data type uses 16 consecutive bits of data
memory that are not separately addressable to
hold a value in the range of 0 to +65,535 (FFFF).

DWORD

Double
Word

Has the same characteristics as a single word data
type, except that it uses 32 consecutive bits in
data memory instead of only 16 bits.

BCD-4

Four-Digit
Binary
Coded
Decimal

Four-digit BCD numbers use 16-bit data memory
locations.  Each BCD digit uses four bits and can
represent  numbers  between  0 and  9.    This BCD
coding  of  the  16  bits  has  a  value  range  of  0  to
9999.

REAL

Floating-
Point

Real  numbers  use  two  consecutive  16-bit
memory  locations.    The  range  of  numbers  that
can be stored in this format is ± 1.401298E-45 to
± 3.402823E+38.  See  the  next  page  for  more
information.

INT

Signed
Integer

Signed integer data uses 16-bit memory
locations. Signed integers are represented in 2's
complement notation. Bit 16 is the sign bit, (0 =
positive,

negative).

Range is -32,768 to +32,767.

DINT

Double
Precision
Signed
Integer

Double  precision  signed  integers  data  uses  two
consecutive  16-bit  memory  locations.  They  are
represented in 2's complement notation. Bit 32 is
the sign bit, (0 = positive, 1 = negative). The range
is
-2,147,483,648 to +2,147,483,647.

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22.5.1

Real Numbers (Floating Point)

The REAL data type, which can be used for some Math functions and Numerical functions, is
actually floating point data. Floating-point numbers are stored in single precision
IEEE-standard format. This format requires 32 bits, which occupy two (adjacent) 16-bit PLC
words.

Figure 239

For example, if the floating-point number occupies registers %R0005 and %R0006, then
%R0005 is the least significant register and %R0006 is the most significant register.

The range of numbers that can be stored in this format is from ± 1.401298E

–

45 to

± 3.402823E+38 and the number zero.

22.5.2

Errors in Real Numbers and Operations

Overflow occurs when a number greater than 3.402823E+38 or less than -3.402823E+38 is
generated by a REAL function. The ok output of the function is set OFF; and the result is set
to positive infinity (for a number greater than 3.402823E+38) or negative infinity (for a
number less than

–

3.402823E+38). You can determine where this occurs by testing the

sense of the ok output.

POS_INF

= 7F800000h

–

IEEE positive infinity representation in hex.

NEG_INF

= FF800000h

–

IEEE negative infinity representation in hex.

If the infinities produced by overflow are used as operands to other REAL functions, they
may cause an undefined result. This result is referred to as NaN (Not a Number). For
example, the result of adding positive infinity to negative infinity is undefined. When the
ADD_REAL function is invoked with positive infinity and negative infinity as its operands, it
produces NaN for its result.

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Chapter 23:

Instruction Set Reference

This section is a reference to the functions in the VersaMax Nano PLC and Micro PLC
Instruction Set:

Bit Operation Functions

Logical AND, Logical OR

Exclusive OR, Logical Invert (NOT)

Shift Right/Shift Left

Rotate Right/Rotate Left

Bit Test, Bit Set, Bit Clear

Masked Compare

Bit Position

Bit Sequencer

Control Functions

Do I/O

Call

End

Comment

Jump

Master Control Relay

Drum Sequencer

Service Request (see Chapter 24:)

PID (see Chapter 26:)

Communication

MODBUS_TCP_RW (see Chapter

14:)

Data Move Functions

Move

Block Move

Block Clear

Shift Register

Communication Request

Data Type Conversion Functions

Convert to BCD-4

Convert to Signed Integer

Convert to Double Precision Signed

Integer

Convert to Real

Convert Real to Word

Truncate Real Number

Math and Numerical Functions

Add, Subtract, Multiply, divide

Modulo Division

Scaling

Square Root

Trigonometric Functions

Logarithmic/Exponential

Functions

Convert Radians / Degrees

Motion Functions (See Chapter 19:)

Find Home

Go Home

Jogging

Blending

Stop Motion

Relational Functions

Equal

Not Equal

Greater Than

Less Than

Greater or Equal

Less or Equal

Range

Relay Functions

Contacts, Coils

Fault and No Fault Contacts

Alarm Contacts

Table Functions

Array Move

Timer and Counter Functions

Time-tick Contacts

On Delay Stopwatch Timer

On Delay Timer

Off Delay Timer

Up Counter

Down Counter

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23.1

Bit Operation Functions

The Bit Operation functions perform comparison, logical, and move operations on bit
strings. The Bit Operation functions are:

•

Logical AND

•

Logical OR

•

Exclusive OR

•

Logical Invert (NOT)

•

Shift Right/Shift Left

•

Rotate Right/Rotate Left

•

Bit Test

•

Bit Set, Bit Clear

•

Masked Compare

•

Bit Position

•

Bit Sequencer

23.1.1

Data Lengths for the Bit Operation functions

The Logical AND, OR, XOR, and NOT (Invert) functions operate on a single word of data.
The other Bit Operation functions may operate on up to 256 words.

All Bit Operation functions require Word-type data. However, they operate on data as a
continuous string of bits, with bit 1 of the first word being the Least Significant Bit (LSB).
The last bit of the last word is the Most Significant Bit (MSB).  For example, if you specified
three words of data beginning at reference %R0100, it would be operated on as 48
contiguous bits.

%R0100 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1



bit 1 (LSB)

%R0101 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

%R0102 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33



(MSB)

Overlapping input and output reference address ranges in multi-word functions is not
recommended, it can produce unexpected results.

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23.1.2

Bit Operation Functions
Logical AND, Logical OR

Each scan that power is received, a Logical AND or Logical OR function examines each bit in
bit string IN1 and the corresponding bit in bit string IN2, beginning at the least significant
bit in each. A string length of 256 words can be selected.

Logical AND

If both bits examined by the Logical AND function are 1, a 1 is placed in the corresponding
location in output string Q. If either or both bits are 0, a 0 is placed in string Q in that location.
The Logical AND function can be used to build masks or screens, where only certain bits are
passed through (bits opposite a 1 in the mask), and all other bits are set to 0. The Logical
AND function can also be used to clear an area of word memory by ANDing the bits with
another bit string known to contain all 0s. The IN1 and IN2 bit strings specified may overlap.

Logical OR

If  either  or  both  bits  examined  by  the  Logical  OR  function  is  1,  a  1  is  placed  in  the
corresponding location in output string Q.  If both bits are 0, a 0 is placed in string Q in that
location. The Logical OR function can be used to combine strings or to control many outputs
with one simple logical structure.  The Logical OR function is the equivalent of two relay
contacts in parallel multiplied by the number of bits in the string.  It can be used to drive
indicator lamps directly from input states, or to superimpose blinking conditions on status
lights.

Figure 240

Parameters of the Logical AND and Logical OR Functions

Input/
Output

Choices

Description

enable

flow

When the function is enabled, the operation is
performed.

I, Q, M, T, S, G, R, AI, AQ, constant Constant or reference for the first word of the first

string.

I, Q, M, T, S, G, R, AI, AQ, constant Constant or reference for the first word of the

second string.

flow, none

The OK output is energized whenever enable is
energized.

I, Q, M, T, SA, SB, SC (not S), G, R,
AI, AQ

Output Q contains the result of the operation.

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Example of the Logical AND Function

In the example, when input %I0001 is set, the 16-bit strings represented by nicknames
WORD1 and WORD2 are examined. The results of the Logical AND are placed in output
string RESULT.

Figure 241

23.1.3

Bit Operation Functions
Exclusive OR

The Exclusive OR function compares each bit in bit string IN1 with the corresponding bit in
string IN2. If the bits are different, a 1 is placed in the corresponding position in the output
bit string.

Figure 242

Each scan that power is received, the Exclusive OR function examines each bit in string IN1
and the corresponding bit in string IN2, beginning at the least significant bit in each. For
each two bits examined, if only one is 1, then a 1 is placed in the corresponding location in
bit string Q. The Exclusive OR function passes power flow to the right whenever power is
received.

If string IN2 and output string Q begin at the same reference, a 1 placed in string IN1 will
cause the corresponding bit in string IN2 to alternate between 0 and 1, changing state with
each scan as long as power is received. Longer cycles can be programmed by pulsing the
power flow to the function at twice the desired rate of flashing; the power flow pulse should
be one scan long (one-shot type coil or self-resetting timer).

The Exclusive OR function is useful for quickly comparing two-bit strings, or to blink a group
of bits at the rate of one ON state per two scans.

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Parameters of the Exclusive OR Function

Input/
Output

Choices

Description

enable

flow

When the function is enabled, the operation is
performed.

IN1

I, Q, M, T, S, G, R, AI, AQ,
constant

Constant or reference for the first word to be XORed.

IN2

I, Q, M, T, S, G, R, AI, AQ,
constant

Constant or reference for the second word to be
XORed.

flow, none

The OK output is energized whenever enable is
energized.

I, Q, M, T, SA, SB, SC (not S), G, R,
AI, AQ

Output Q contains the result of the operation.

Example

In the example, whenever %I0001 is set, the bit string represented by the nickname WORD3
is cleared (set to all zeros).

Figure 243

IN1 (WORD3)

0 0

IN2 (WORD3)

0 0

Q (WORD3)

0 0

23.1.4

Bit Operation Functions
Logical Invert (NOT)

The Logical Invert (NOT) function sets the state of each bit in the output bit string Q to the
opposite of the state of the corresponding bit in bit string IN1.

All bits are altered on each scan that power is received, making output string Q the logical
complement of IN1. The function passes power flow to the right whenever power is
received. A length of 256 words can be selected.

Figure 244

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Parameters of the Logical Invert Function

Input/
Output

Choices

Description

enable

flow

When the function is enabled, the operation is
performed.

I, Q, M, T, S, G, R, AI, AQ, constant Constant or reference for the word to be negated.

flow, none

The OK output is energized whenever enable is
energized.

I, Q, M, T, SA, SB, SC (not S), G, R,
AI, AQ

Output Q contains the result of the operation.

Example

In the example, whenever input %I0001 is set, the bit string represented by the nickname
TAC is set to the inverse of bit string CAT.

Figure 245

23.1.5

Bit Operation Functions
Shift Bits Right, Shift Bits Left

The Shift Left function shifts all the bits in a word or group of words to the left by a specified
number of places. When the shift occurs, the specified number of bits is shifted out of the
output string to the left. As bits are shifted out of the high end of the string, the same
number of bits is shifted in at the low end.

MSB

LSB



The Shift Right function is used to shift all the bits in a word or group of words a specified
number of places to the right.  When the shift occurs, the specified number of bits is shifted
out of the output string to the right.  As bits are shifted out of the low end of the string, the
same number of bits is shifted in at the high end.

MSB

LSB

→

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A string length of 1 to 256 words can be selected for either function.

Figure 246

If the number of bits to be shifted (N) is greater than the number of bits in the array * 16,
the array (Q) is filled with copies of the input bit (B1), and the input bit is copied to the output
power flow (B2). If the number of bits to be shifted is zero, then no shifting is performed;
the input array is copied into the output array; and input bit (B1) is copied into the power
flow.

The bits being shifted into the beginning of the string are specified via input parameter B1.
If a length greater than 1 has been specified as the number of bits to be shifted, each of the
bits is filled with the same value (0 or 1). This can be:

•

The Boolean output of another program function.

•

All 1s. To do this, use the special reference nickname ALW_ON as a permissive to
input B1.

•

All 0s. To do this, use the special reference nickname ALW_OFF as a permissive to
input B1.

The function passes power flow to the right, unless the number of bits specified to be shifted
is zero.

Output Q is the shifted copy of the input string.  If you want the input string to be shifted,
the output parameter Q must use the same memory location as the input parameter IN.
The entire shifted string is written on each scan that power is received.  Output B2 is the last
bit shifted out.  For example, if four bits were shifted, B2 would be the fourth bit shifted out.

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Bit Operation Functions
Shift Bits Right, Shift Bits Left

Parameters of the Shift Right / Left Functions

Input/
Output

Choices

Description

enable

flow

When the function is enabled, the shift is performed.

I, Q, M, T, S, G, R, AI, AQ

IN contains the first word to be shifted.

I, Q, M, T, G, R, AI, AQ, constant N contains the number of places (bits) that the array is

to be shifted.

flow

B1 contains the bit value to be shifted into the array.

flow, none

B2 contains the bit value of the last bit shifted out of
the array.

I, Q, M, T, SA, SB, SC, G, R, AI,
AQ

Output Q contains the first word of the shifted array.

Example

In the example, whenever input %I0001 is set, the output bit string contained in the memory
location represented by the nickname WORD2 is made a copy of the bits in location
WORD1. The output string is left-shifted by 8 bits, as specified by the input LENGTH. The
resulting open bits at the beginning of the output string are set to the value of %I0002.

Figure 247

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23.1.6

Bit Operation Functions
Rotate Bits Right, Rotate Bits Left

The Rotate Left function rotates all the bits in a string a specified number of places to the
left. When rotation occurs, the specified number of bits is rotated out of the input string to
the left and back into the string on the right.

The Rotate Right function rotates the bits in the string to the right. When rotation occurs,
the specified number of bits is rotated out of the input string to the right and back into the
string on the left.

A length of 1 to 256 words can be selected for either function. The number of places to
rotate must be more than zero and less than the number of bits in the string.

The Rotate Bits function passes power flow to the right, unless the number of bits specified
to be rotated is greater than the total length of the string or is less than zero. The result is
placed in output string Q. If you want the input string to be rotated, the output parameter
Q must use the same memory location as the input parameter IN. The entire rotated string
is written on each scan that power is received.

Figure 248

Parameters of the Rotate Bits Right / Left Functions

Input/
Output

Choices

Description

enable

flow

When the function is enabled, the rotation is performed.

I, Q, M, T, S, G, R, AI, AQ

IN contains the first word to be rotated.

I, Q, M, T, G, R, AI, AQ,
constant

N contains the number of places the array is to be rotated.

flow, none

The OK output is energized when the rotation is energized,
and the rotation length is not greater than the array size.

I, Q, M, T, SA, SB, SC, G, R,
AI, AQ

Output Q contains the first word of the rotated array.

Example

In the example, whenever input %I0001 is set, the input bit string in location %R0001 is
rotated 3 bits. The result is placed in %R0002. The input bit string %R0001 is not changed by
the function. If the same reference is used for IN and Q, a rotation will occur in place.

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Figure 249

23.1.7

Bit Operation Functions
Bit Test

The Bit Test function tests a bit within a bit string to determine whether that bit is currently
1 or 0. The result of the test is placed in output Q.

Each sweep power is received, the Bit Test function sets its output Q to the same state as
the specified bit. If a register rather than a constant is used to specify the bit number, the
same function block can test different bits on successive sweeps.

If the value of BIT is outside the range (1 < BIT < (16 * length) ), then Q is set OFF.

A string length of 1 to 256 words can be selected.

Figure 250

Parameters of the Bit Test Function

Input/
Output

Choices

Description

enable

flow

When the function is enabled, the bit test is performed.

I, Q, M, T, S, G, R, AI, AQ

IN contains the first word of the data to be operated on.

BIT

I, Q, M, T, G, R, AI, AQ,
constant

BIT contains the bit number of IN that should be tested.
Valid range is (1 < BIT < (16 * length)).

flow, none

Output Q is energized if the bit tested was a 1.

Example

In the example, whenever input %I0001 is set, the bit at the location contained in reference
PICKBIT is tested. The bit is part of string PRD_CDE. If it is 1, output Q passes power flow
and the coil %Q0001 is turned on.

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Figure 251

23.1.8

Bit Operation Functions
Bit Set and Bit Clear

The Bit Set function sets a bit in a bit string to 1. The Bit Clear function sets a bit in a string
to 0.

Each sweep that power is received, the function sets the specified bit. If a variable (register)
rather than a constant is used to specify the bit number, the same function block can set
different bits on successive sweeps.

A string length of 1 to 256 words can be selected. The function passes power flow to the
right, unless the value for BIT is outside the range (1 < BIT < (16 * length) ); then, OK is set
OFF.

Figure 252

Parameters of the Bit Set and Bit Clear Functions

Input/
Output

Choices

Description

enable

flow

When the function is enabled, the bit operation is performed.

I, Q, M, T, SA, SB, SC, G,
R, AI, AQ

IN contains the first word of the data to be operated on.

BIT

I, Q, M, T, G, R, AI, AQ,
constant

BIT contains the bit number of IN that should be set or
cleared. Valid range is (1 < BIT < (16 * length) ).

flow, none

The OK output is energized whenever the bit input is valid
and enable is energized.

EMERSON PACSystems VersaMax MICRO PLC & NANO PLC. USER MANUAL (2019) - page 29