Atmel ATmega328P 8-bit AVR Microcontroller. DATASHEET (2015)

• Bit 7 - SPMIE: SPM Interrupt Enable

When the SPMIE bit is written to one, and the I-bit in the status register is set (one), the SPM ready interrupt will be enabled.

The SPM ready interrupt will be executed as long as the SELFPRGEN bit in the SPMCSR register is cleared.

• Bit 6 - RWWSB: Read-While-Write Section Busy

When a self-programming (page erase or page write) operation to the RWW section is initiated, the RWWSB will be set

(one) by hardware. When the RWWSB bit is set, the RWW section cannot be accessed. The RWWSB bit will be cleared if

the RWWSRE bit is written to one after a self-programming operation is completed. Alternatively the RWWSB bit will

automatically be cleared if a page load operation is initiated.

• Bit 5 - Res: Reserved Bit

This bit is a reserved bit in the Atmel^® ATmega328P and always read as zero.

• Bit 4 - RWWSRE: Read-While-Write Section Read Enable

When programming (page erase or page write) to the RWW section, the RWW section is blocked for reading (the RWWSB

will be set by hardware). To re-enable the RWW section, the user software must wait until the programming is completed

(SELFPRGEN will be cleared). Then, if the RWWSRE bit is written to one at the same time as SELFPRGEN, the next SPM

instruction within four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while the flash is

busy with a page erase or a page write (SELFPRGEN is set). If the RWWSRE bit is written while the flash is being loaded,

the flash load operation will abort and the data loaded will be lost.

• Bit 3 - BLBSET: Boot Lock Bit Set

If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four clock cycles sets boot lock

bits and memory lock bits, according to the data in R0. The data in R1 and the address in the Z-pointer are ignored. The

BLBSET bit will automatically be cleared upon completion of the lock bit set, or if no SPM instruction is executed within four

clock cycles.

An LPM instruction within three cycles after BLBSET and SELFPRGEN are set in the SPMCSR register, will read either the

lock bits or the fuse bits (depending on Z0 in the Z-pointer) into the destination register. See Section 26.8.9 “Reading the

Fuse and Lock Bits from Software” on page 235 for details.

• Bit 2 - PGWRT: Page Write

If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four clock cycles executes page

write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer. The data in

R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is executed

within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.

• Bit 1 - PGERS: Page Erase

If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four clock cycles executes page

erase. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will

auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted

during the entire page write operation if the NRWW section is addressed.

• Bit 0 - SELFPRGEN: Self Programming Enable

This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLBSET,

PGWRT or PGERS, the following SPM instruction will have a special meaning, see description above. If only SELFPRGEN

is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the

Z-pointer. The LSB of the Z-pointer is ignored. The SELFPRGEN bit will auto-clear upon completion of an SPM instruction,

or if no SPM instruction is executed within four clock cycles. During page erase and page write, the SELFPRGEN bit remains

high until the operation is completed.

Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower five bits will have no effect.

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27.

Memory Programming

27.1

Program And Data Memory Lock Bits

The Atmel^® ATmega328P provides six lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain

the additional features listed in Table 27-2. The lock bits can only be erased to “1” with the chip erase command.The

ATmega328P has no separate boot loader section. The SPM instruction is enabled for the whole flash if the SELFPRGEN

fuse is programmed (“0”), otherwise it is disabled.

Table 27-1. Lock Bit Byte⁽¹⁾

Lock Bit Byte

Bit No

Description

Default Value

1 (unprogrammed)

BLB12⁽²⁾

Boot lock bit

1 (unprogrammed)

BLB11⁽²⁾

Boot lock bit

1 (unprogrammed)

BLB02⁽²⁾

Boot lock bit

1 (unprogrammed)

BLB01⁽²⁾

Boot lock bit

1 (unprogrammed)

LB2

Lock bit

1 (unprogrammed)

LB1

Lock bit

1 (unprogrammed)

Notes:

“1” means unprogrammed, “0” means programmed

Only on ATmega328P.

Table 27-2. Lock Bit Protection Modes⁽¹⁾⁽²⁾

Memory Lock Bits

Protection Type

LB Mode

LB2

LB1

No memory lock features enabled.

Further programming of the flash and EEPROM is disabled in parallel and

serial programming mode. The fuse bits are locked in both serial and parallel

programming mode.⁽¹⁾

Further programming and verification of the flash and EEPROM is disabled in

parallel and serial programming mode. The boot lock bits and fuse bits are

locked in both serial and parallel programming mode.⁽¹⁾

Notes:

Program the fuse bits and boot lock bits before programming the LB1 and LB2.

“1” means unprogrammed, “0” means programmed

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Table 27-3. Lock Bit Protection Modes⁽¹⁾⁽²⁾

BLB0 Mode

BLB02

BLB01

No restrictions for SPM or LPM accessing the application section.

SPM is not allowed to write to the application section.

SPM is not allowed to write to the application section, and LPM executing

from the boot loader section is not allowed to read from the application

section. If interrupt vectors are placed in the boot loader section, interrupts

are disabled while executing from the application section.

LPM executing from the boot loader section is not allowed to read from the

application section. If interrupt vectors are placed in the boot loader section,

interrupts are disabled while executing from the application section.

BLB1 Mode

BLB12

BLB11

No restrictions for SPM or LPM accessing the boot loader section.

SPM is not allowed to write to the boot loader section.

SPM is not allowed to write to the boot loader section, and LPM executing

from the application section is not allowed to read from the boot loader

section. If interrupt vectors are placed in the application section, interrupts

are disabled while executing from the boot loader section.

LPM executing from the application section is not allowed to read from the

boot loader section. If interrupt vectors are placed in the application section,

interrupts are disabled while executing from the boot loader section.

Notes:

Program the fuse bits and boot lock bits before programming the LB1 and LB2.

“1” means unprogrammed, “0” means programmed

27.2

Fuse Bits

The ATmega328P has three fuse bytes. Table 27-4 - Table 27-7 on page 244 describe briefly the functionality of all the fuses

and how they are mapped into the fuse bytes. Note that the fuses are read as logical zero, “0”, if they are programmed.

Table 27-4. Extended Fuse Byte for ATmega328P

Extended Fuse Byte

Bit No

Description

Default Value

–

SELFPRGEN

Self programming enable

1 (unprogrammed)

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Table 27-5. Extended Fuse Byte for ATmega328P

Extended Fuse Byte

Bit No.

Description

Default Value

–

BODLEVEL2⁽¹⁾

Brown-out detector trigger level

1 (unprogrammed)

BODLEVEL1⁽¹⁾

Brown-out detector trigger level

1 (unprogrammed)

BODLEVEL0⁽¹⁾

Brown-out detector trigger level

1 (unprogrammed)

Note:

See Table 28-5 on page 262 for BODLEVEL fuse decoding.

Table 27-6. Fuse High Byte for ATmega328P

High Fuse Byte

Bit No.

Description

Default Value

RSTDISBL⁽¹⁾

External reset disable

1 (unprogrammed)

DWEN

debugWIRE enable

1 (unprogrammed)

Enable serial program and data

0 (programmed, SPI programming

SPIEN⁽²⁾

downloading

enabled)

WDTON⁽³⁾

Watchdog timer always On

1 (unprogrammed)

EEPROM memory is preserved

1 (unprogrammed), EEPROM not

EESAVE

through the chip erase

reserved

Select boot size

BOOTSZ1

(see Table 26-7 on page 239

0 (programmed)⁽⁴⁾

for details)

Select boot size

BOOTSZ0

(see Table 26-7 on page 239

0 (programmed)⁽⁴⁾

for details)

BOOTRST

Select reset vector

1 (unprogrammed)

Notes:

See Section 13.3.2 “Alternate Functions of Port C” on page 68 for description of RSTDISBL fuse.

The SPIEN fuse is not accessible in serial programming mode.

See Section 10.9.2 “WDTCSR - Watchdog Timer Control Register” on page 47 for details.

The default value of BOOTSZ[1:0] results in maximum boot size. See Section 27-11 “Pin Name Mapping” on

page 246.

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Table 27-7. Fuse Low Byte

Low Fuse Byte

Bit No.

Description

Default Value

CKDIV8⁽²⁾⁴

Divide clock by 8

0 (programmed)

CKOUT⁽³⁾

Clock output

1 (unprogrammed)

SUT1

Select start-up time

1 (unprogrammed)⁽¹⁾

SUT0

Select start-up time

0 (programmed)⁽¹⁾

CKSEL3

Select clock source

0 (programmed)⁽²⁾

CKSEL2

Select clock source

0 (programmed)⁽²⁾

CKSEL1

Select clock source

1 (unprogrammed)⁽²⁾

CKSEL0

Select clock source

0 (programmed)

Notes:

The default value of SUT1..0 results in maximum start-up time for the default clock source. See Table 8-11 on

page 30 for details.

The default setting of CKSEL3..0 results in internal RC oscillator at 8MHz. See Table 8-10 on page 30 for

details.

The CKOUT fuse allows the system clock to be output on PORTB0. See Section 8.9 “Clock Output Buffer” on

page 31 for details.

See Section 8.11 “System Clock Prescaler” on page 32 for details.

The status of the fuse bits is not affected by chip erase. Note that the fuse bits are locked if lock bit1 (LB1) is programmed.

program the fuse bits before programming the lock bits.

27.2.1

Latching of Fuses

The fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect

until the part leaves programming mode. This does not apply to the EESAVE fuse which will take effect once it is

programmed. The fuses are also latched on power-up in normal mode.

27.3

Signature Bytes

All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial

and parallel mode, also when the device is locked. The three bytes reside in a separate address space. For the Atmel^®

ATmega328P the signature bytes are given in Table 27-8.

Table 27-8. Device ID

Signature Bytes Address

Part

0x000

0x001

0x002

ATmega328P

0x1E

0x95

0x0F

27.4

Calibration Byte

The Atmel ATmega328P has a byte calibration value for the internal RC oscillator. This byte resides in the high byte of

address 0x000 in the signature address space. During reset, this byte is automatically written into the OSCCAL register to

ensure correct frequency of the calibrated RC oscillator.

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27.5

Page Size

Table 27-9. No. of Words in a Page and No. of Pages in the Flash

Device

Flash Size

Page Size

PCWORD

No. of Pages

PCPAGE

PCMSB

16K words

ATmega328P

64 words

PC[5:0]

256

PC[13:6]

(32K bytes)

Table 27-10. No. of Words in a Page and No. of Pages in the EEPROM

Device

EEPROM Size

Page Size

PCWORD

No. of Pages

PCPAGE

EEAMSB

ATmega328P

1K bytes

4 bytes

EEA[1:0]

256

EEA[9:2]

27.6

Parallel Programming Parameters, Pin Mapping, and Commands

This section describes how to parallel program and verify flash program memory, EEPROM data memory, memory lock bits,

and fuse bits in the ATmega328P. Pulses are assumed to be at least 250ns unless otherwise noted.

27.6.1

Signal Names

In this section, some pins of the Atmel^® ATmega328P are referenced by signal names describing their functionality during

parallel programming, see Figure 27-1 and Table 27-11 on page 246. Pins not described in the following table are referenced

by pin names.

The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse. The bit coding is shown in

Table 27-13 on page 246.

When pulsing WR or OE, the command loaded determines the action executed. The different commands are shown in Table

27-14 on page 246.

Figure 27-1. Parallel Programming

+ 4.5V to 5.5V

RDY/BSY

PD1

VCC

PD2

+ 4.5V to 5.5V

PD3

AVCC

BS1

PD4

XA0

PD5

PC[1:0]:PB[5:0]

DATA

XA1

PD6

PAGEL

PD7

+12V

RESET

BS2

PC2

XTAL1

GND

Note:

V_CC to 0.3V < AV_CC < V_CC + 0.3V, however, AV_CC should always be within 4.5 to 5.5V

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Table 27-11. Pin Name Mapping

Signal Name in

Programming Mode

Pin Name

I/O

Function

0: Device is busy programming, 1: Device is ready for

RDY/BSY

PD1

new command

PD2

Output enable (active low)

PD3

Write pulse (active low)

BS1

PD4

Byte select 1 (“0” selects low byte, “1” selects high byte)

XA0

PD5

XTAL action Bit 0

XA1

PD6

XTAL action Bit 1

PAGEL

PD7

Program memory and EEPROM data page load

Byte select 2 (“0” selects low byte, “1” selects 2’nd high

BS2

PC2

byte)

DATA

{PC[1:0]: PB[5:0]}

I/O

Bi-directional data bus (output when OE is low)

Table 27-12. Pin Values Used to Enter Programming Mode

Symbol

Value

PAGEL

Prog_enable[3]

XA1

Prog_enable[2]

XA0

Prog_enable[1]

BS1

Prog_enable[0]

Table 27-13. XA1 and XA0 Coding

XA1

XA0

Action when XTAL1 is Pulsed

Load flash or EEPROM address (high or low address byte determined by BS1).

Load data (high or low data byte for flash determined by BS1).

Load command

No action, idle

Table 27-14. Command Byte Bit Coding

Command Byte

Command Executed

1000 0000

Chip erase

0100 0000

Write fuse bits

0010 0000

Write lock bits

0001 0000

Write flash

0001 0001

Write EEPROM

0000 1000

Read signature bytes and calibration byte

0000 0100

Read fuse and lock bits

0000 0010

Read flash

0000 0011

Read EEPROM

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27.7

Parallel Programming

27.7.1

Enter Programming Mode

The following algorithm puts the device in parallel (high-voltage) programming mode:

Set prog_enable pins listed in Table 27-12 on page 246 to “0000”, RESET pin to 0V and V_CC to 0V.

Apply 4.5 to 5.5V between V_CC and GND.

Ensure that V_CC reaches at least àpçV within the next 20µs.

Wait 20 to 60µs, and apply 11.5 to 12.5V to RESET.

Keep the Prog_enable pins unchanged for at least10µs after the high-voltage has been applied to ensure the

prog_enable signature has been latched.

Wait at least 300µs before giving any parallel programming commands.

Exit programming mode by power the device down or by bringing RESET pin to 0V.

If the rise time of the V_CC is unable to fulfill the requirements listed above, the following alternative algorithm can be used.

Set prog_enable pins listed in Table 27-12 on page 246 to “0000”, RESET pin to 0V and V_CC to 0V.

Apply 4.5 to 5.5V between V_CC and GND.

Monitor V_CC, and as soon as V_CC reaches 0.9 to 1.1V, apply 11.5 to 12.5V to RESET.

Keep the prog_enable pins unchanged for at least 10µs after the high-voltage has been applied to ensure the

prog_enable signature has been latched.

Wait until V_CC actually reaches 4.5 to 5.5V before giving any parallel programming commands.

Exit programming mode by power the device down or by bringing RESET pin to 0V.

27.7.2

Considerations for Efficient Programming

The loaded command and address are retained in the device during programming. For efficient programming, the following

should be considered.

● The command needs only be loaded once when writing or reading multiple memory locations.

● Skip writing the data value 0xFF, that is the contents of the entire EEPROM (unless the EESAVE fuse is programmed)

and flash after a chip erase.

● Address high byte needs only be loaded before programming or reading a new 256 word window in flash or 256 byte

EEPROM. This consideration also applies to signature bytes reading.

27.7.3

Chip Erase

The chip erase will erase the flash and EEPROM⁽¹⁾memories plus lock bits. The lock bits are not reset until the program

memory has been completely erased. The fuse bits are not changed. A chip erase must be performed before the flash

and/or EEPROM are reprogrammed.

Note:

The EEPRPOM memory is preserved during chip erase if the EESAVE fuse is programmed.

Load command “chip erase”

Set XA1, XA0 to “10”. This enables command loading.

Set BS1 to “0”.

Set DATA to “1000 0000”. This is the command for chip erase.

Give XTAL1 a positive pulse. This loads the command.

Give WR a negative pulse. This starts the chip erase. RDY/BSY goes low.

Wait until RDY/BSY goes high before loading a new command.

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27.7.4

Programming the Flash

The Flash is organized in pages, see Table 27-9 on page 245. When programming the flash, the program data is latched into

a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes

how to program the entire flash memory:

A. Load Command “Write Flash”

Set XA1, XA0 to “10”. This enables command loading.

Set BS1 to “0”.

Set DATA to “0001 0000”. This is the command for write flash.

Give XTAL1 a positive pulse. This loads the command.

B. Load Address Low byte

Set XA1, XA0 to “00”. This enables address loading.

Set BS1 to “0”. This selects low address.

Set DATA = Address low byte (0x00 - 0xFF).

Give XTAL1 a positive pulse. This loads the address low byte.

C. Load Data Low Byte

Set XA1, XA0 to “01”. This enables data loading.

Set DATA = Data low byte (0x00 - 0xFF).

Give XTAL1 a positive pulse. This loads the data byte.

D. Load Data High Byte

Set BS1 to “1”. This selects high data byte.

Set XA1, XA0 to “01”. This enables data loading.

Set DATA = Data high byte (0x00 - 0xFF).

Give XTAL1 a positive pulse. This loads the data byte.

E. Latch Data

Set BS1 to “1”. This selects high data byte.

Give PAGEL a positive pulse. This latches the data bytes. (See Figure 27-3 on page 249 for signal waveforms)

F. Repeat B through E until the entire buffer is filled or until all data within the page is loaded.

While the lower bits in the address are mapped to words within the page, the higher bits address the pages within the flash.

This is illustrated in Figure 27-2 on page 249. Note that if less than eight bits are required to address words in the page

(Page size < 256), the most significant bit(s) in the address low byte are used to address the page when performing a page

write.

G. Load Address High byte

Set XA1, XA0 to “00”. This enables address loading.

Set BS1 to “1”. This selects high address.

Set DATA = Address high byte (0x00 - 0xFF).

Give XTAL1 a positive pulse. This loads the address high byte.

H. Program Page

Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSY goes low.

Wait until RDY/BSY goes high (See Figure 27-3 on page 249 for signal waveforms).

I. Repeat B through H until the entire flash is programmed or until all data has been programmed.

J. End page programming

1. Set XA1, XA0 to “10”. This enables command loading.

Set DATA to “0000 0000”. This is the command for No operation.

Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset.

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27.7.5

Programming the EEPROM

The EEPROM is organized in pages, see Table 27-10 on page 245. When programming the EEPROM, the program data is

latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for

the EEPROM data memory is as follows (refer to Section 27.7.4 “Programming the Flash” on page 248 for details on

command, address and data loading):

A: Load Command “0001 0001”.

G: Load Address High Byte (0x00 - 0xFF).

B: Load Address Low Byte (0x00 - 0xFF).

C: Load Data (0x00 - 0xFF).

E: Latch data (give PAGEL a positive pulse).

K: Repeat 3 through 5 until the entire buffer is filled.

L: Program EEPROM page

Set BS1 to “0”.

Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY goes low.

Wait until to RDY/BSY goes high before programming the next page (See Figure 27-4 for signal waveforms).

Figure 27-4. Programming the EEPROM Waveforms

DATA

0x11

ADDR. HIGH

ADDR. LOW

DATA

ADDR. LOW

DATA

XA1

XA0

BS1

XTAL1

RDY/BSY

RESET +12V

PAGEL

BS2

27.7.6

Reading the Flash

The algorithm for reading the flash memory is as follows (refer to Section 27.7.4 “Programming the Flash” on page 248 for

details on command and address loading):

A: Load command “0000 0010”.

G: Load address high byte (0x00 - 0xFF).

B: Load address low byte (0x00 - 0xFF).

Set OE to “0”, and BS1 to “0”. The flash word low byte can now be read at DATA.

Set BS1 to “1”. The flash word high byte can now be read at DATA.

Set OE to “1”.

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27.7.7

Reading the EEPROM

The algorithm for reading the EEPROM memory is as follows (refer to Section 27.7.4 “Programming the Flash” on page 248

for details on command and address loading):

A: Load command “0000 0011”.

G: Load address high byte (0x00 - 0xFF).

B: Load address low byte (0x00 - 0xFF).

Set OE to “0”, and BS1 to “0”. The EEPROM data byte can now be read at DATA.

Set OE to “1”.

27.7.8

Programming the Fuse Low Bits

The algorithm for programming the fuse low bits is as follows (refer to Section 27.7.4 “Programming the Flash” on page 248

for details on command and data loading):

A: Load command “0100 0000”.

C: Load data low byte. Bit n = “0” programs and bit n = “1” erases the fuse bit.

Give WR a negative pulse and wait for RDY/BSY to go high.

27.7.9

Programming the Fuse High Bits

The algorithm for programming the fuse high bits is as follows (refer to Section 27.7.4 “Programming the Flash” on page 248

for details on command and data loading):

A: Load command “0100 0000”.

C: Load data low byte. Bit n = “0” programs and bit n = “1” erases the fuse bit.

Set BS1 to “1” and BS2 to “0”. This selects high data byte.

Give WR a negative pulse and wait for RDY/BSY to go high.

Set BS1 to “0”. This selects low data byte.

27.7.10 Programming the Extended Fuse Bits

The algorithm for programming the extended fuse bits is as follows (refer to Section 27.7.4 “Programming the Flash” on page

248 for details on command and data loading):

1. A: Load command “0100 0000”.

2. C: Load data low byte. Bit n = “0” programs and bit n = “1” erases the fuse bit.

3. Set BS1 to “0” and BS2 to “1”. This selects extended data byte.

4. Give WR a negative pulse and wait for RDY/BSY to go high.

5. Set BS2 to “0”. This selects low data byte.

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Figure 27-5. Programming the FUSES Waveforms

Write Fuse Low byte

Write Fuse High byte

Write Extended Fuse byte

DATA

0x40

DATA

0x40

DATA

0x40

DATA

XA1

XA0

BS1

BS2

XTAL1

RDY/BSY

RESET +12V

PAGEL

27.7.11 Programming the Lock Bits

The algorithm for programming the lock bits is as follows (refer to Section 27.7.4 “Programming the Flash” on page 248 for

details on command and data loading):

A: Load command “0010 0000”.

C: Load data low byte. Bit n = “0” programs the lock bit. If LB mode 3 is programmed (LB1 and LB2 is

programmed), it is not possible to program the boot lock bits by any external programming mode.

Give WR a negative pulse and wait for RDY/BSY to go high.

The lock bits can only be cleared by executing chip erase.

27.7.12 Reading the Fuse and Lock Bits

The algorithm for reading the fuse and lock bits is as follows (refer to Section 27.7.4 “Programming the Flash” on page 248

for details on command loading):

A: Load command “0000 0100”.

Set OE to “0”, BS2 to “0” and BS1 to “0”. The status of the fuse low bits can now be read at DATA (“0” means

programmed).

Set OE to “0”, BS2 to “1” and BS1 to “1”. The status of the fuse high bits can now be read at DATA (“0” means

programmed).

Set OE to “0”, BS2 to “1”, and BS1 to “0”. The status of the extended fuse bits can now be read at DATA (“0”

means programmed).

Set OE to “0”, BS2 to “0” and BS1 to “1”. The status of the lock bits can now be read at DATA (“0” means

programmed).

Set OE to “1”.

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Figure 27-6. Mapping between BS1, BS2 and the Fuse and Lock Bits During Read

Fuse Low Byte

Extended Fuse Byte

DATA

BS2

Lock Bits

BS1

Fuse High Byte

BS2

27.7.13 Reading the Signature Bytes

The algorithm for reading the signature bytes is as follows (refer to Section 27.7.4 “Programming the Flash” on page 248 for

details on command and address loading):

A: Load command “0000 1000”.

B: Load address low byte (0x00 - 0x02).

Set OE to “0”, and BS1 to “0”. The selected signature byte can now be read at DATA.

Set OE to “1”.

27.7.14 Reading the Calibration Byte

The algorithm for reading the calibration byte is as follows (refer to Section 27.7.4 “Programming the Flash” on page 248 for

details on command and address loading):

A: Load command “0000 1000”.

B: Load address low byte, 0x00.

Set OE to “0”, and BS1 to “1”. The calibration byte can now be read at DATA.

Set OE to “1”.

27.7.15 Parallel Programming Characteristics

For characteristics of the parallel programming, see Section 28.10 “Parallel Programming Characteristics” on page 265.

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27.8

Serial Downloading

Both the flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND.

The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, the programming enable

instruction needs to be executed first before program/erase operations can be executed. NOTE, in Table 27-15, the pin

mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal SPI interface.

Figure 27-7. Serial Programming and Verify⁽¹⁾

+ 1.8V to 5.5V

VCC

+ 1.8V to 5.5V⁽²⁾

MOSI

AVCC

MISO

SCK

XTAL1

RESET

GND

Notes:

If the device is clocked by the internal oscillator, it is no need to connect a clock source to the XTAL1 pin.

V_CC - 0.3V < AV_CC < V_CC + 0.3V, however, AV_CC should always be within 2.7 to 5.5V

When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the serial mode

ONLY) and there is no need to first execute the chip erase instruction. The chip erase operation turns the content of every

memory location in both the program and EEPROM arrays into 0xFF.

Depending on CKSEL fuses, a valid clock must be present. The minimum low and high periods for the serial clock (SCK)

input are defined as follows:

Low:

> 2 CPU clock cycles for f_ck < 12MHz, 3 CPU clock cycles for f_ck ≥ 12MHz

High:

> 2 CPU clock cycles for f_ck < 12MHz, 3 CPU clock cycles for f_ck ≥ 12MHz

27.8.1

Serial Programming Pin Mapping

Table 27-15. Pin Mapping Serial Programming

Symbol

Pins

I/O

Description

MOSI

PB3

Serial data in

MISO

PB4

Serial data out

SCK

PB5

Serial clock

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27.8.2

Serial Programming Algorithm

When writing serial data to the Atmel^® ATmega328P, data is clocked on the rising edge of SCK.

When reading data from the ATmega328P, data is clocked on the falling edge of SCK. See Figure 27-9 on page 257 for

timing details.

To program and verify the ATmega328P in the serial programming mode, the following sequence is recommended (see

serial programming instruction set in Table 27-17 on page 256):

Power-up sequence:

Apply power between V_CC and GND while RESET and SCK are set to “0”. In some systems, the programmer can

not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse of at

least two CPU clock cycles duration after SCK has been set to “0”.

Wait for at least 20ms and enable serial programming by sending the programming enable serial instruction to pin

MOSI.

The serial programming instructions will not work if the communication is out of synchronization. When in sync.

the second byte (0x53), will echo back when issuing the third byte of the programming enable instruction. Whether

the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give

RESET a positive pulse and issue a new programming enable command.

The flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the 6

LSB of the address and data together with the load program memory page instruction. To ensure correct loading

of the page, the data low byte must be loaded before data high byte is applied for a given address. The program

memory page is stored by loading the write program memory page instruction with the 7 MSB of the address. If

polling (RDY/BSY) is not used, the user must wait at least t_{WD_FLASH} before issuing the next page (see

Table 27-16). Accessing the serial programming interface before the flash write operation completes can result in

incorrect programming.

A: The EEPROM array is programmed one byte at a time by supplying the address and data together with the

appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is

written. If polling (RDY/BSY) is not used, the user must wait at least t_{WD_EEPROM} before issuing the next byte (see

Table 27-16). In a chip erased device, no 0xFFs in the data file(s) need to be programmed.

B: The EEPROM array is programmed one page at a time. The memory page is loaded one byte at a time by

supplying the 6 LSB of the address and data together with the Load EEPROM memory page instruction. The

EEPROM memory page is stored by loading the write EEPROM memory page instruction with the 7 MSB of the

address. When using EEPROM page access only byte locations loaded with the Load EEPROM memory page

instruction is altered. The remaining locations remain unchanged.

If polling (RDY/BSY) is not used, the used must wait at least t_{WD_EEPROM} before issuing the next byte (see

Table 27-16). In a chip erased device, no 0xFF in the data file(s) need to be programmed.

Any memory location can be verified by using the read instruction which returns the content at the selected

address at serial output MISO.

At the end of the programming session, RESET can be set high to commence normal operation.

Power-off sequence (if needed):

Set RESET to “1”.

Turn V_CC power off.

Table 27-16. Typical Wait Delay Before Writing the Next Flash or EEPROM Location

Symbol

Minimum Wait Delay

t_{WD_FLASH}

4.5ms

t_{WD_EEPROM}

3.6ms

t_{WD_ERASE}

9.0ms

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27.8.3

Serial Programming Instruction set

Table 27-17 and Figure 27-8 on page 257 describes the Instruction set.

Table 27-17. Serial Programming Instruction Set (Hexadecimal Values)

Instruction Format

Instruction/Operation

Byte 1

Byte 2

Byte 3

Byte4

Programming enable

$AC

$53

$00

Chip erase (program memory/EEPROM)

$AC

$80

$00

Poll RDY/BSY

$F0

$00

data byte out

Load instructions

Load extended address byte⁽¹⁾

$4D

$00

Extended adr

$00

Load program memory page, high byte

$48

$00

adr LSB

high data byte in

Load program memory page, low byte

$40

$00

adr LSB

low data byte in

Load EEPROM memory page (page

$C1

$00

0000 000aa

data byte in

access)

Read instructions

Read program memory, high byte

$28

adr MSB

adr LSB

high data byte out

Read program memory, low byte

$20

adr MSB

adr LSB

low data byte out

Read EEPROM memory

$A0

0000 00aa

aaaa aaaa

data byte out

Read lock bits

$58

$00

data byte out

Read signature byte

$30

$00

0000 000aa

data byte out

Read fuse bits

$50

$00

data byte out

Read fuse high bits

$58

$08

$00

data byte out

Read extended fuse bits

$50

$08

$00

data byte out

Read calibration byte

$38

$00

data byte out

Write instructions⁽⁶⁾

Write program memory page

$4C

adr MSB

adr LSB

$00

Write EEPROM memory

$C0

0000 00aa

aaaa aaaa

data byte in

Write EEPROM memory page (page

$C2

0000 00aa

aaaa aa00

$00

access)

Write lock bits

$AC

$E0

$00

data byte in

Write fuse bits

$AC

$A0

$00

data byte in

Write fuse high bits

$AC

$A8

$00

data byte in

Write extended fuse bits

$AC

$A4

$00

data byte in

Notes:

Not all instructions are applicable for all parts.

a = address.

Bits are programmed ‘0’, unprogrammed ‘1’.

To ensure future compatibility, unused fuses and lock bits should be unprogrammed (‘1’).

Refer to the corresponding section for fuse and lock bits, calibration and signature bytes and page size.

Instructions accessing program memory use a word address. This address may be random within the page

range.

See http://www.atmel.com/avr for application notes regarding programming and programmers.

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If the LSB in RDY/BSY data byte out is ‘1’, a programming operation is still pending. Wait until this bit returns ‘0’ before the

next instruction is carried out.

Within the same page, the low data byte must be loaded prior to the high data byte.

After data is loaded to the page buffer, program the EEPROM page, see Figure 27-8.

Figure 27-8. Serial Programming Instruction Example

Serial Programming Instruction

Load Program Memory Page (High/Low Byte)/

Write Program Memory Page/

Load EEPROM Memory Page (page access)

Write EEPROM Memory Page

Byte 1

Byte 2

Byte 3

Byte 4

Byte 1

Byte 2

Byte 3

Byte 4

Adr MBS

Adr LBS

Adr MBS

Adr LBS

Bit 15 B

Page Buffer

Page Offset

Page 0

Page 1

Page 2

Page Number

Page N-1

Program Memory/

EEPROM Memory

27.8.4

SPI Serial Programming Characteristics

Figure 27-9. Serial Programming Waveforms

SERIAL DATA INPUT

MSB

LSB

(MOSI)

SERIAL DATA OUTPUT

MSB

LSB

(MISO)

SERIAL CLOCK INPUT

(SCK)

SAMPLE

For characteristics of the SPI module see Section 28.7 “SPI Timing Characteristics” on page 262.

ATmega328P [DATASHEET]

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28.

Electrical Characteristics

All DC/AC characteristics contained in this datasheet are based on characterization of Atmel^® ATmega328P AVR^®

microcontroller manufactured in an automotive process technology.

28.1

Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating

only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Parameters

Min.

Typ.

Max.

Unit

Operating temperature

-55

+125

°C

Storage temperature

-65

+150

°C

Voltage on any pin except RESET with respect

-0.5

V_CC + 0.5

to ground

Voltage on RESET with respect to ground

-0.5

+13.0

Maximum operating voltage

6.0

DC current per I/O pin

40.0

DC current V_CC and GND pins

200.0

Injection current at V_CC = 0V

±5.0⁽¹⁾

Injection current at V_CC = 5V

±1.0

Note:

Maximum current per port = ±30mA

28.2

DC Characteristics

TA = -40°C to +125°C, VCC = 2.7V to 5.5V (unless otherwise noted)

Parameter

Condition

Symbol

Min.

Typ.

Max.

Unit

Input low voltage, except

V_CC = 2.7V to 5.5V

V_IL

-0.5

0.3V_CC(1)

XTAL1 and RESET pin

Input high voltage, except

V_CC = 2.7V to 5.5V

VIH

0.6V_CC(2)

V_CC + 0.5

XTAL1 and RESET pins

Input low voltage,

V_CC = 2.7V to 5.5V

V_IL1

-0.5

0.1V_CC(1)

XTAL1 pin

Input high voltage,

V_CC = 2.7V to 5.5V

V_IH1

0.7V_CC(2)

V_CC + 0.5

XTAL1 pin

Notes:

“Max” means the highest value where the pin is guaranteed to be read as low

“Min” means the lowest value where the pin is guaranteed to be read as high

Although each I/O port can sink more than the test conditions (20mA at V_CC = 5V, 10mA at V_CC = 3V) under steady

state conditions (non-transient), the following must be observed:

ATmega328P:

1] The sum of all I_OL, for ports C0 - C5, should not exceed 100mA.

2] The sum of all I_OL, for ports B0 - B5, D5 - D7, XTAL1, XTAL2 should not exceed 100mA.

3] The sum of all I_OL, for ports D0 - D4, should not exceed 100mA.

If I_OL exceeds the test condition, V_OL may exceed the related specification. Pins are not guaranteed to sink current

greater than the listed test condition.

Although each I/O port can source more than the test conditions (20mA at V_CC = 5V, 10mA at V_CC = 3V) under steady

state conditions (non-transient), the following must be observed:

ATmega328P:

1] The sum of all I_OH, for ports C0 - C5, D0- D4, should not exceed 150mA.

2] The sum of all I_OH, for ports B0 - B5, D5 - D7, XTAL1, XTAL2 should not exceed 150mA.

If II_OH exceeds the test condition, V_OH may exceed the related specification. Pins are not guaranteed to source current

greater than the listed test condition.

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28.2

DC Characteristics (Continued)

TA = -40°C to +125°C, VCC = 2.7V to 5.5V (unless otherwise noted)

Parameter

Condition

Symbol

Min.

Typ.

Max.

Unit

Input low voltage,

V_CC = 2.7V to 5.5V

V_IL2

-0.5

0.1V_CC(1)

RESET pin

Input high voltage,

V_CC = 2.7V to 5.5V

V_IH2

0.9V_CC(2)

V_CC + 0.5

RESET pin

I_OL = 20mA, V_CC = 5V

0.8

Output low voltage⁽³⁾

V_OL

I_OL = 5mA, V_CC

= 3V

0.5

I_OH = -20mA, V_CC = 5V

4.1

Output high voltage⁽⁴⁾

V_OH

I_OH = -10mA, V_CC

= 3V

2.3

Input leakage

V_CC = 5.5V, pin low

I_IL

µA

Current I/O pin

(absolute value)

Input leakage

V_CC = 5.5V, pin high

I_IH

µA

Current I/O pin

(absolute value)

Reset pull-up resistor

R_RST

k

I/O pin pull-up resistor

R_PU

k

Analog comparator

0.4V < V_in < V_cc - 0.5

VACIO

Input offset voltage

(absolute value)

Analog comparator

V_CC = 5V

I_ACLK

-50

+50

Input leakage current

Vin = VCC/2

Notes:

“Max” means the highest value where the pin is guaranteed to be read as low

“Min” means the lowest value where the pin is guaranteed to be read as high

Although each I/O port can sink more than the test conditions (20mA at V_CC = 5V, 10mA at V_CC = 3V) under steady

state conditions (non-transient), the following must be observed:

ATmega328P:

1] The sum of all I_OL, for ports C0 - C5, should not exceed 100mA.

2] The sum of all I_OL, for ports B0 - B5, D5 - D7, XTAL1, XTAL2 should not exceed 100mA.

3] The sum of all I_OL, for ports D0 - D4, should not exceed 100mA.

If I_OL exceeds the test condition, V_OL may exceed the related specification. Pins are not guaranteed to sink current

greater than the listed test condition.

Although each I/O port can source more than the test conditions (20mA at V_CC = 5V, 10mA at V_CC = 3V) under steady

state conditions (non-transient), the following must be observed:

ATmega328P:

1] The sum of all I_OH, for ports C0 - C5, D0- D4, should not exceed 150mA.

2] The sum of all I_OH, for ports B0 - B5, D5 - D7, XTAL1, XTAL2 should not exceed 150mA.

If II_OH exceeds the test condition, V_OH may exceed the related specification. Pins are not guaranteed to source current

greater than the listed test condition.

ATmega328P [DATASHEET]

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28.3

DC Characteristics

TA = -40°C to +125°C, VCC = 2.7V to 5.5V (unless otherwise noted)

Parameter

Condition

Symbol

Min.

Typ.⁽²⁾

Max.

Units

Active 4MHz, V_CC = 3V

1.5

2.4

Active 8MHz, V_CC = 5V

5.2

Active 16MHz, V

CC = 5V

9.2

Power supply current⁽¹⁾

Idle 4MHz, V_CC = 3V

0.25

0.6

Idle 8MHz, V_CC = 5V

1.0

1.6

Idle 16MHz, V_CC = 5V

1.9

2.8

WDT enabled, V_CC = 3V

µA

WDT enabled, V_CC = 5V

µA

Power-down mode⁽³⁾

WDT disabled, VCC = 3V

µA

WDT disabled, V_CC = 5V

µA

Notes:

Values with Section 9.10 “Minimizing Power Consumption” on page 36 enabled (0xFF).

Typical values at 25°C.

The current consumption values include input leakage current.

28.4

Speed Grades

Figure 28-1. Maximum Frequency

16MHz

8MHz

Safe Operating Area

2.7V

4.5V

5.5V

28.5

Clock Characteristics

28.5.1

Calibrated Internal RC Oscillator Accuracy

Table 28-1. Calibration Accuracy of Internal RC Oscillator

Frequency

V_CC

Temperature

Calibration Accuracy

Factory

25°C

±2%

8.0MHz

Calibration

2.7V to 5.5V

-40°C to +125°C

±14%

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28.5.2

Watchdog Oscillator Accuracy

Table 28-2. Accuracy of Watchdog Oscillator

Parameter

Condition

Symbol

Min

Typ

Max

Unit

Watchdog oscillator frequency

V_cc = 2.7 to 5.5V

Fwdt

128

180

KHz

28.5.3

External Clock Drive Waveforms

Figure 28-2. External Clock Drive Waveforms

t_CHCX

t_CLCH

t_CHCL

V_IH1

V_IL1

t_CLCX

t_CLCL

28.5.4

External Clock Drive

Table 28-3. External Clock Drive

VCC = 2.7 to 5.5V

V_CC= 4.5 to 5.5V

Parameter

Symbol

Min.

Max.

Min.

Max.

Unit

Oscillator frequency

1/t_CLCL

MHz

High time

t_CHCX

Low time

t_CLCX

Rise time

t_CLCH

1.6

0.5

Fall time

t_CHCL

1.6

0.5

Change in period from one

t_CLCL

clock cycle to the next

Note:

All DC/AC characteristics contained in this datasheet are based on characterization of ATmega328P AVR

microcontroller manufactured in an automotive process technology.

28.6

System and Reset Characteristics

Table 28-4. Reset, Brown-out and Internal Voltage Characteristics

Parameter

Symbol

Min

Typ

Max

Unit

Brown-out detector hysteresis

V_HYST

Bandgap reference voltage

VCC = 5V

V_BG

1.0

1.1

1.2

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Table 28-5. BODLEVEL Fuse Coding⁽¹⁾

BODLEVEL 2:0 Fuses

Min V_BOT

Typ V_BOT

Max V_BOT

Units

111

BOD disabled

110

Reserved

101

2.5

2.7

2.9

100

4.0

4.3

4.6

011

010

Reserved

001

000

Note:

VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case,

the device is tested down to V_CC = V_BOT during the production test. This guarantees that a brown-out reset will

occur before V_CC drops to a voltage where correct operation of the microcontroller is no longer guaranteed.

The test is performed using BODLEVEL = 100 and BODLEVEL = 101 for ATmega328P.

28.7

SPI Timing Characteristics

See Figure 28-3 on page 263 and Figure 28-4 on page 263 for details.

Table 28-6.

SPI Timing Parameters

Description

Mode

Min

Typ

Max

SCK period

Master

See Table 18-5 on page 141

SCK high/low

Master

50% duty cycle

Rise/fall time

Master

3.6

Setup

Master

Hold

Master

Out to SCK

Master

0.5  t_sck

SCK to out

Master

SCK to out high

Master

SS low to out

Slave

SCK period

Slave

4  t_ck

SCK high/low⁽¹⁾

Slave

2  t_ck

Rise/fall time

Slave

1600

Setup

Slave

Hold

Slave

t_ck

SCK to out

Slave

SCK to SS high

Slave

SS high to tri-state

Slave

SS low to SCK

Slave

Notes:

In SPI programming mode the minimum SCK high/low period is:

- 2 t_CLCL for f_CK < 12MHz

- 3 t_CLCL for f_CK > 12MHz

All AC/AC characteristics contained in this datasheet are based on characterization of ATmega328P AVR

microcontroller manufactured in an automotive process technology.

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28.8

2-wire Serial Interface Characteristics

Table 28-7 describes the requirements for devices connected to the 2-wire serial bus. The Atmel^® ATmega328P 2-wire serial

interface meets or exceeds these requirements under the noted conditions.

Timing symbols refer to Figure 28-5 on page 265.

Table 28-7.

2-wire Serial Bus Requirements

Parameter

Condition

Symbol

Min

Max

Units

Input low-voltage

V_IL

-0.5

0.3 V_CC

Input high-voltage

V_IH

0.7 V_CC

CC + 0.5

Hysteresis of schmitt trigger inputs

V_hys(1)

0.05 V_CC(2)

Output low-voltage

3mA sink current

V_OL(1)

0.4

Rise time for both SDA and SCL

t_r(1)

20 + 0.1C_b(3)(2)

300

Output fall time from V_IHmin to V_ILmax

10pF < C_b < 400pF⁽³⁾

t_of(1)

20 + 0.1C_b(3)(2)

250

Spikes suppressed by input filter

t_SP(1)

50⁽²⁾

Input current each I/O pin

0.1V_CC < V_i < 0.9V_CC

I_i

-10

µA

Capacitance for each I/O pin

C_i(1)

SCL clock frequency

⁽⁴⁾ >max(16f_SCL, 250kHz)⁽⁵⁾

f_SCL

400

kHz

V_CC

– 0.4V

----------------------------

---------------



SCL ≤ 100kHz

3mA

Value of pull-up resistor

V_CC

- 0.4V

----------------------------

-------------



SCL > 100kHz

3mA

4.0

µs

SCL ≤ 100kHz

Hold time (repeated) START condition

t_HD;STA

0.6

µs

SCL > 100kHz

4.7

µs

SCL ≤ 100kHz

Low period of the SCL clock

t_LOW

1.3

µs

SCL > 100kHz

4.0

µs

SCL ≤ 100kHz

High period of the SCL clock

t_HIGH

0.6

µs

SCL > 100kHz

4.7

µs

Set-up time for a repeated START

SCL ≤ 100kHz

t_SU;STA

condition

0.6

µs

SCL > 100kHz

3.45

µs

SCL ≤ 100kHz

Data hold time

t_HD;DAT

0.9

µs

SCL > 100kHz

250

SCL ≤ 100kHz

Data setup time

t_SU;DAT

100

SCL > 100kHz

4.0

µs

SCL ≤ 100kHz

Setup time for STOP condition

t_SU;STO

0.6

µs

SCL > 100kHz

4.7

µs

Bus free time between a STOP and

SCL ≤ 100kHz

t_BUF

START condition

1.3

µs

SCL > 100kHz

Notes:

In Atmel ATmega328P, this parameter is characterized and not 100% tested.

Required only for f_SCL > 100kHz.

C_b = capacitance of one bus line in pF.

f_CK = CPU clock frequency

This requirement applies to all Atmel ATmega328P 2-wire serial interface operation. Other devices connected

to the 2-wire serial bus need only obey the general f_SCL requirement.

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Figure 28-5. 2-wire Serial Bus Timing

t_of

t_HIGH

t_LOW

SCL

t_SU,STA

t_HD,STA

t_HD,DAT

SU,DAT

SU,STO

SDA

BUF

28.9

ADC Characteristics

Table 28-8. ADC Characteristics

Parameter

Condition

Symbol

Min

Typ

Max

Unit

-40°C +125°C / 2.70 to 5.50V

Resolution

bits

ADC clock = 200kHz

Absolute accuracy

V_cc = 4.0V,V_REF= 4.0V

TUE

2.2

3.5

LSB

Integral non linearity

V_cc = 4.0V, V_REF= 4.0V

INL

0.6

1.5

LSB

Differential non linearity

V_cc = 4.0V, V_REF= 4.0V

DNL

0.3

0.7

LSB

Gain error

V_cc = 4.0V, V_REF= 4.0V

-3.5

+3.5

LSB

Offset error

V_cc = 4.0V, V_REF= 4.0V

-3.5

+3.5

LSB

Clock frequency

200

kHz

Analog supply voltage

AV_CC

V_cc - 0.3

V_cc + 0.3

Reference voltage

V_REF

1.0

AV_CC

Input voltage

Vin

GND

V_REF

Internal voltage reference

V_cc = 5v

Vint

1.0

1.1

1.2

Reference input resistance

R_ref

22.4

41.6

k

Analog input resistance

Rain

100

M

28.10

Parallel Programming Characteristics

Table 28-9. Parallel Programming Characteristics, V_CC = 5V ±10%

Parameter

Symbol

Min

Typ

Max

Units

Programming enable voltage

V_PP

11.5

12.5

Programming enable current

I_PP

250

µA

Data and control valid before XTAL1 high

t_DVXH

XTAL1 low to XTAL1 high

t_XLXH

200

XTAL1 pulse width high

t_XHXL

150

Data and control hold after XTAL1 low

t_XLDX

XTAL1 low to WR low

t_XLWL

XTAL1 low to PAGEL high

t_XLPH

PAGEL low to XTAL1 high

t_PLXH

150

Notes:

t_WLRHis valid for the write flash, write EEPROM, write fuse bits and write lock bits commands.

t_{WLRH_CE}is valid for the chip erase command.

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Table 28-9. Parallel Programming Characteristics, V_CC = 5V ±10% (Continued)

Parameter

Symbol

Min

Typ

Max

Units

BS1 valid before PAGEL high

t_BVPH

PAGEL pulse width high

t_PHPL

150

BS1 hold after PAGEL low

t_PLBX

BS2/1 hold after WR low

t_WLBX

PAGEL low to WR low

t_PLWL

BS1 valid to WR low

t_BVWL

WR pulse Width low

t_WLWH

150

WR low to RDY/BSY low

t_WLRL

µs

WR low to RDY/BSY high⁽¹⁾

t_WLRH

3.7

4.5

WR low to RDY/BSY high for chip erase⁽²⁾

t_{WLRH_CE}

7.5

XTAL1 low to OE low

t_XLOL

BS1 valid to DATA valid

t_BVDV

250

OE low to DATA valid

t_OLDV

250

OE high to DATA tri-stated

t_OHDZ

250

Notes:

t_WLRHis valid for the write flash, write EEPROM, write fuse bits and write lock bits commands.

t_{WLRH_CE}is valid for the chip erase command.

Figure 28-6. Parallel Programming Timing, Including some General Timing Requirements

t_XLWL

XTAL1

t_XHXL

t_DVXH

t_XLDX

Data and Control

(DATA, XA0/1, BS1, BS2)

t_BVPH

t_PLBX

t_BVWL

t_WLBX

PAGEL

t_PHPL

t_WLWH

t_PLWL

t_WLRL

RDY/BSY

t_WLRH

266

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Figure 28-7. Parallel Programming Timing, Loading Sequence with Timing Requirements⁽¹⁾

Load Address

Load Data

Load Address

(Low Byte)

(High Byte)

Load Data

(Low Byte)

t_XLXH

t_XLPH

t_PLXH

XTAL1

BS1

PAGEL

DATA

ADDR0 (Low Byte)

DATA (Low Byte)

DATA (High Byte)

ADDR1 (Low Byte)

XA0

XA1

Note:

The timing requirements shown in Figure 28-6 (i.e., t_DVXH, t_XHXL, and t_XLDX) also apply to loading operation.

Figure 28-8. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements⁽¹⁾

Load Address

Read Data

Load Address

(Low Byte)

(High Byte)

(Low Byte)

t_XLOL

XTAL1

t_BVDV

BS1

t_OLDV

OHDZ

DATA

ADDR0 (Low Byte)

DATA (Low Byte)

DATA (High Byte)

ADDR1 (Low Byte)

XA0

XA1

Note:

The timing requirements shown in Figure 28-6 on page 266 (i.e., t_DVXH, t_XHXL, and t_XLDX) also apply to reading

operation.

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29.

Typical Characteristics

The data contained in this section are characterized values of actual automotive silicon. Unless otherwise specified, the data

contained in this chapter are for -40° to 125°C.

The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption

measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A square wave

generator with rail-to-rail output is used as clock source.

All Active- and idle current consumption measurements are done with all bits in the PRR register set and thus, the

corresponding I/O modules are turned off. Also the analog comparator is disabled during these measurements. The “supply

current of IO modules” shows the additional current consumption compared to I_CC active and I_CC idle for every I/O module

controlled by the power reduction register. See Section 9.9 “Power Reduction Register” on page 36 for details.

The power consumption in power-down mode is independent of clock selection.

The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O pins,

switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and

frequency.

The current drawn from capacitive loaded pins may be estimated (for one pin) as C_L V_CC  f where C_L = load capacitance,

V_CC = operating voltage and f = average switching frequency of I/O pin.

The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at

frequencies higher than the ordering code indicates.

The difference between current consumption in power-down mode with watchdog timer enabled and power-down mode with

watchdog timer disabled represents the differential current drawn by the watchdog timer.

29.1

ATmega328P Typical Characteristics

29.1.1

Active Supply Current

Figure 29-1. Active Supply Current versus Frequency

5.5

5.0

4.5

3.6

3.3

3.0

2.7

Frequency (MHz)

268

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30.

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0xFF)

Reserved

(0xFE)

Reserved

(0xFD)

Reserved

(0xFC)

Reserved

(0xFB)

Reserved

(0xFA)

Reserved

(0xF9)

Reserved

(0xF8)

Reserved

(0xF7)

Reserved

(0xF6)

Reserved

(0xF5)

Reserved

(0xF4)

Reserved

(0xF3)

Reserved

(0xF2)

Reserved

(0xF1)

Reserved

(0xF0)

Reserved

(0xEF)

Reserved

(0xEE)

Reserved

(0xED)

Reserved

(0xEC)

Reserved

(0xEB)

Reserved

(0xEA)

Reserved

(0xE9)

Reserved

(0xE8)

Reserved

(0xE7)

Reserved

(0xE6)

Reserved

(0xE5)

Reserved

(0xE4)

Reserved

(0xE3)

Reserved

(0xE2)

Reserved

(0xE1)

Reserved

(0xE0)

Reserved

(0xDF)

Reserved

(0xDE)

Reserved

(0xDD)

Reserved

(0xDC)

Reserved

(0xDB)

Reserved

(0xDA)

Reserved

Notes:

For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory

addresses should never be written.

I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In

these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.

Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVR^®, the CBI and

SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status

flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.

When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing

I/O registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega328P

is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in opcode

for the IN and OUT instructions. For the extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and

LD/LDS/LDD instructions can be used.

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30.

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0xD9)

Reserved

(0xD8)

Reserved

(0xD7)

Reserved

(0xD6)

Reserved

(0xD5)

Reserved

(0xD4)

Reserved

(0xD3)

Reserved

(0xD2)

Reserved

(0xD1)

Reserved

(0xD0)

Reserved

(0xCF)

Reserved

(0xCE)

Reserved

(0xCD)

Reserved

(0xCC)

Reserved

(0xCB)

Reserved

(0xCA)

Reserved

(0xC9)

Reserved

(0xC8)

Reserved

(0xC7)

Reserved

(0xC6)

UDR0

USART I/O data register

159

(0xC5)

UBRR0H

USART baud rate register high

162

(0xC4)

UBRR0L

USART baud rate register low

162

(0xC3)

Reserved

UCSZ01

UCSZ00 /

(0xC2)

UCSR0C

UMSEL01

UMSEL00

UPM01

UPM00

USBS0

UCPOL0

161/172

/UDORD0

UCPHA0

(0xC1)

UCSR0B

RXCIE0

TXCIE0

UDRIE0

RXEN0

TXEN0

UCSZ02

RXB80

TXB80

160

(0xC0)

UCSR0A

RXC0

TXC0

UDRE0

FE0

DOR0

UPE0

U2X0

MPCM0

159

(0xBF)

Reserved

(0xBE)

Reserved

(0xBD)

TWAMR

TWAM6

TWAM5

TWAM4

TWAM3

TWAM2

TWAM1

TWAM0

201

(0xBC)

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

TWIE

199

(0xBB)

TWDR

2-wire serial interface data register

200

(0xBA)

TWAR

TWA6

TWA5

TWA4

TWA3

TWA2

TWA1

TWA0

TWGCE

201

(0xB9)

TWSR

TWS7

TWS6

TWS5

TWS4

TWS3

TWPS1

TWPS0

200

(0xB8)

TWBR

2-wire serial interface bit rate register

198

(0xB7)

Reserved

(0xB6)

ASSR

EXCLK

AS2

TCN2UB

OCR2AUB

OCR2BUB

TCR2AUB

TCR2BUB

133

(0xB5)