EMERSON PACSystems VersaMax MICRO PLC & NANO PLC. USER MANUAL (2019) - page 24

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Module

I1 to I4

I5 to I6

I7 to I8

I9 to I12

I13

I14 to I16

I17 to I24

I25 to I40

IC200UDR164

100nS

IC200UDR064

100nS

IC200UDD164

100nS

IC200UDD064

100nS

IC200UEX009

20mS

IC200UEX010

20mS

IC200UEX011

200nS

IC200UEX012

200nS

IC200UEX014

200nS

IC200UEX122

200nS

IC200UEX013

200nS

IC200UEX015

200nS

IC200UEI016

3mS

IC200UEX209

20mS

IC200UEX210

20mS

IC200UEX211

200nS

IC200UEX212

200nS

IC200UEX214

200nS

IC200UEX222

200nS

IC200UEX213

200nS

IC200UEX215

200nS

IC200UEX164

100nS

IC200UEX064

100nS

IC200UEX364

100nS

IC200UEX264

100nS

IC200UEI008

3mS

IC200UEC208

200nS

IC200UEC108

200nS

IC200UEC008

200nS

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17.12

Analog Potentiometer Input Filtering

17.12.1

Input Settings

VersaMax Micro-14, Micro-23, and Micro-28 PLCs have two potentiometers, located below
the Run/Stop switch, that can be used to manually set input values that are stored in %AI16
and %AI17. The left potentiometer controls %AI16, and the right one controls %AI17.

Filter Control Reference

Due to the nature of analog input, the values seen in %AI16 and %AI17 will have some
fluctuation. This variation could make these inputs less suitable for certain applications. The
Micro PLC uses an averaging filter that samples the values of these inputs once per sweep.
When a selected number of samples has been read, it averages them and stores the result
in %AI16 and %AI17.

The value in memory reference %AQ1 controls the number of samples to be averaged,
calculated as follows:

Number of samples = 2

%AQ1

The value in %AQ1 can be from 0 to 7 (indicating 0 through 128 samples).

For example, if 4 is placed in %AQ1, 16 samples are averaged to determine the values to
place in %AI16 and %AI17. If 5 is placed in %AQ1, 32 samples are averaged.

The analog value from the potentiometer is not reported until the number of sweeps
determined by the value in AQ1 has occurred. If you want to receive a value from the
potentiometer on every sweep, including the first sweep, %AQ1 must contain 0.

17.12.2

Default Filter Time

The default value in %AQ1 is 4, meaning that 16 samples will be averaged.

17.12.3

Limitations of Analog Potentiometer Input Filtering

As with any filter, the longer the filter time (i.e., the more samples that are taken), the longer
the response time. Although the maximum value of 7 could be used in %AQ1, this value
might cause a long response time on larger programs. For example, if the sweep time of a
program is 100ms, and if the potentiometer value is changed, the new value would not
show up for 12.8 seconds.

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Chapter 18:

High-Speed Counter, PWM, and
Pulse Train Operation

This chapter describes the configuration and operation of the High-Speed Counter, Pulse-
Width Modulated Output, and Pulse Train Output features of VersaMax Micro and Nano
PLCs.

•

Overview

•

HSC/PWM/PTO Channels

•

Type A Counter Operation

•

Type B Counter Operation

•

High-Speed Counter Outputs

•

PWM Outputs

•

Pulse Train Outputs

•

Pulse Train with Ramp

•

COMMREQs for HSC/PWM/PTO Functions

•

HSC Application Examples

For a Micro-20, Micro-40, or Micro-64 (Release 3.6 or later) PLC, individual channels can
perform the basic Motion Control functions of: Jogging, Homing, Blended Move, and Stop
Motion. Details of these features are provided in Chapter 19:.

18.1

Overview

All VersaMax Nano PLCs and Micro PLCs with DC inputs are configurable for a mix of High-
Speed Counting features. Nano PLCs and Micro PLCs with DC outputs can also be configured
with Pulse-Width Modulation, Pulse Train, and Pulse Train with Ramp features.

For added flexibility, the operating parameters of these features can be fine-tuned during
operation by including special function blocks in the application program.

Micro-20, Micro-40 and Release 3.6 and later Micro-64 PLCs provide Jog, Homing, and
Blended (multi-velocity move) functionality commanded by function blocks in the
application program. They also feature configurable 32-bit resolution for both Type A and
Type B counters.

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18.1.1

Operation at Power-up and Mode Change

High-Speed Counters (except PTO with Ramp) run independently of the PLC application
program. When the PLC goes from Run to Stop mode, the High-Speed Counters continue
to operate (as specified in the configuration). High-Speed Counters remain in running mode
through a power cycle. If a High-Speed Counter is running when power is lost, it will start
again as soon as power is restored. When power is cycled or the PLC is placed in Run mode,
the Accumulator register is loaded with the configured Preload value.

If the PLC goes into Stop mode when the PTO with Ramp is running, the ramp output stops
immediately.

If a new configuration has been stored to the PLC, the PLC continues with the existing
HSC/PTO/PWM/Pulse Train with Ramp/Motion Features configuration. When the PLC is
switched to Run mode, the HSC begins using the new configuration and the Preload value
is placed in the Accumulator register.

18.1.2

Basic Setup

There are three basic steps to setting up High-Speed Counter, PWM, and Pulse Train
features.

•

With the configuration software, enable each feature you want to use.

•

If you want a counter to control an output you must enable the output, also using
the configuration software.

•

Finally, you can provide application program control over operation of the output by
setting or clearing its associated Enable Output bit from the program or in the data
tables. For example, if a High-Speed Counter is configured with its output enabled
and its Output Enable bit is set, it will control the output. The Output Enable bits are
assigned to fixed reference addresses: Q505 through Q508.

A sample ladder logic rung that sets the Output Enable bit for a High-Speed Counter is
shown below.

Figure 183

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18.2

HSC/PWM/PTO Channels

A Micro PLC (which has 14

–

64 points) can be set up to have either four 16-bit Type A

counters, or one 16-bit Type A counter and one 16-bit Type B counter. Micro-20, -40, and -
64 PLCs can also be set up to have either four 32-bit Type A counters, or one 32-bit Type A
and one 32-bit Type B counter.

A Nano PLC (which has 10 points) can be set up to have either three 16-bit Type A counters,
or one 16-bit Type A counter and one 16-bit Type B counter).

•

Each channel can be configured for High-Speed Counter, PWM, Standard, Pulse
Train, Pulse Train with Ramping operation (in 16-bit mode) or Motion support (in 32-
bit mode).

•

A channel that uses High-Speed Counter inputs can use its associated output(s) as
either High-Speed Counter or standard output(s).

•

A channel that uses PWM or Pulse Train or Pulse Train with Ramping or Motion
support outputs can use its associated inputs as standard inputs.

•

High-Speed Counter inputs cannot be mixed with PWM, PTO, PTO with Ramping or
Motion support outputs on the same channel.

18.2.1

HSC/PWM/PTO Channels for Micro PLCs (14 Point/ 28
Point)

Channel
Configuration
Choice

Creates
this
Number
of
Channels

Number of Type A
Counters
Configured

Number of Type B
Counters

Number of PWM /
Pulse Train
Outputs

Four Type A

Four

One Type A and
One Type B

Two

For Micro PLCs that have only one DC output, only one PWM or Pulse Train output can be
configured.

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18.2.2

HSC/PWM/PTO Channels for Micro-20, -40, or -64 PLC

The following HSC/PWM/PTO features are available for Micro-20, Micro-40, or Micro-64
(Release 3.6 or later) PLCs:

Channel
Configuration
Choice

Creates
this
Number
of
Channels

Number of Type A
Counters
Configured

Number of Type B
Counters

Number of PWM
/ Pulse
Train/Ramp
Pulse
Train/Motion
Support

Four Type A

Four

One Type A and
One Type B

Two

Four Type A_32 Four

One Type A and
One Type B_32

Two

For Micro PLCs that have only one DC output, only one PWM or Pulse Train/Ramp Pulse Train
Or Motion output can be configured.

Ramp Pulse Train Outputs are available for Four Type A / One Type A and One Type B. Motion
Support is available for Four Type A / One Type A and One Type B in 32-bit mode.

18.2.3

HSC/PWM/PTO Channels for Nano PLCs

Channel
Configuration
Choice

Creates
this
Number
of
Channels

Number of Type A
Counters
Configured

Number of Type B
Counters

Number of PWM
/ Pulse Train
Outputs

Three Type A

Three

One Type A and
One Type B

Two

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18.3

Type A Counter

The Type A counter is one counter that can count up or down. Configurable high and low

limits set the counter’s

range. The Type A counter has an Accumulator register, a Counts

per Timebase register, a Strobe register, high limit, low limit, and ON/OFF Preset values.
These are signed numbers. The values selected for the Preload, Accumulator, On Preset, and
Off Preset registers must be within the counter limits.

Figure 184

18.3.1

Type A Counter Program References

The following program references are used for Type A Counter data. The Clear Strobe and
Clear Preload output bits are used to clear (reset) the Strobe and Preload status bits within
the module (they do not initiate a strobe or preload to the counter).

Counter 1

Counter 2 Counter 3

Counter 4

Count Input

I0001

I0003

I0005

I0007

Preload or Strobe Input

I0002

I0004

I0006

I0008

Strobe Status Bits

I0497

I0498

I0499

I0500

Preload Status

I0501

I0502

I0503

I0504

Output Status

I0505

I0506

I0507

I0508

Counter Output

Q0001

Q0002

Q0003

Q0004

Clear Strobe Bits

Q0497

Q0498

Q0499

Q0500

Clear Preload Bits

Q0501

Q0502

Q0503

Q0504

Enable Output

Q0505

Q0506

Q0507

Q0508

Counts per Timebase Register

AI002

AI003

AI004

AI005

Accumulator Registers: 16-Bit mode AI006

AI008

AI010

AI012

32-Bit mode

AI006-007

AI010-011

AI020-021

AI024-025

Strobe Registers : 16-Bit mode
32-Bit mode

AI007
AI008-009

AI009
AI012-013

AI011
AI 022-023

AI013
AI026-027

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18.3.2

Type A Counter Operation

The counter can either count continuously within its limits, or count to either limit then stop
(one-shot mode). In continuous counting, the Accumulator wraps when the count limit is
reached and continues counting. For example, if the Count Direction is up, when the count
exceeds the High Limit by 1, the Accumulator value wraps to the Low Limit. In one-shot
mode, the counter stops at Limit N+1 for up counters or N-1 for down counters if within the
range.

In the example below, the counter has been configured to count on the low to high
transition of the Pulse input. The Count signal represents an internal signal that indicates
where counting occurs with respect to the pulse input.

Figure 185

High-Speed Counters run independently of the application program. When the PLC goes
from Run to Stop mode, its High-Speed Counters continue to operate. High-Speed Counters
remain in run mode through a power cycle. If a High-Speed Counter is running when power
is lost, it will start again as soon as power is restored. Counters will stop on a store of logic
or configuration and a write to the user storage device. When power is cycled or the PLC is
placed in Run mode, the Accumulator is loaded with the Preload value and the registers start
updating.

18.3.3

Type A High-Speed Counter Operation Details

The Count Pulse input increments or decrements the counter’s accumulator. The count

input can be configured to be positive or negative edge-sensitive. The configured On/Off
Preset values determine when the counter output is activated or deactivated. For example:

Lo Limit = 0

Hi Limit = 200

On Preset = 150

Off Preset = 160

Figure 186: Count Direction = Up

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Figure 187: Count Direction = Down

Depending on the configuration for Preload/Strobe, the Preload/Strobe Input can either
preload a value into the Accumulator or strobe the accumulator value into a register.
Preload/Strobe signals are always positive edge-sensitive.

•

If the Preload/Strobe input is configured as a Preload input, the configured Preload
value is transferred to the Accumulator Register when the input transitions from low
to high. When a preload occurs, the PLC sets the Preload Status bit. The application
program can reset the bit before the next preload.

The Preload input always loads the Accumulator regardless of the state of the
Preload Status bit. The value in the Preload register can be configured to any value

in the counter’s range. This selection is part of the PLC configuration. However, the

value can be changed during operation using a COMMREQ function in the program.
Also, The program can also use a COMMREQ to load an adjustment value to the
Accumulator register. The adjustment value can be between -128 and +127.

•

If the Preload/Strobe Input is configured as a Strobe input, when its Strobe input
signal goes active the PLC places the current value in that

counter’s Accumulator

into its Strobe register. The PLC sets the associated Strobe Status bit to indicate that
a Strobe value was captured. The Strobe value remains in the Strobe register until
the Strobe signal goes active again, at which time it is overwritten by a new value.
The Strobe status bit stays on until the program clears it.

The Strobe input always loads the Strobe register with the Accumulator value
regardless of the state of the Strobe bit. Strobe inputs can be used as Pulse Capture
Inputs by using the Strobe status bits as a latch.

Timebase is a span of time used to measure the rate of counting. For example, the program
could monitor the number of counts that occur in 30 seconds. Timebase is configurable in
1mS increments from 10mS to 65530mS. The Counts-per-Timebase register contains the
number of counts that occurred during the last completed timebase interval. The number
of counts is a signed number. The sign indicates up (+) or down (-) counts. If the configured
timebase is too large, the Counts per Timebase register will lose the overflow values.

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Error Status and Status Code: The program should monitor the Error Status bit %I0512 to
check for error conditions. When this bit is 1, the program can look at the Status Code
register %AI001 to learn what caused the error. After taking any necessary corrective action,
the program logic should clear the error status by clearing the Clear Error output bit

(%Q0512). See “Command Word Error Responses” later in this chapter for more

information.

18.4

Type B Counter

The Type B counter uses two counter input signals for A-Quad-B counting. The phase
relationship between the counter inputs (A & B) determines whether the accumulator is
incremented or decremented on a transition of either counter input.

Figure 188: The count direction is up if A leads B.

Figure 189: The count direction is down if A lags B.

The Type B counter can have one output that is activated based on selected On and Off
preset values.

Figure 190

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The counter counts continuously within its limits. The Accumulator wraps when the count
limit is reached and continues counting. For example, if the Count Direction is up, when the
count exceeds the High Limit by 1, the Accumulator value wraps to the Low Limit.

18.4.1

Type B Counter Program References

The following program references are used for Type B Counter data. The Clear Strobe and
Clear Preload output bits are used to clear (reset) the Strobe and Preload status bits within
the module (they do not initiate a strobe or preload to the counter).

Type B Counter

Count Inputs

Phase 1: I0001
Phase 2: I0003

Preload or Strobe Input

I0006

Strobe Status Bit

I0497

Preload Status Bit

I0501

Counter Output

Q0003

Clear Strobe Bit

Q0497

Clear Preload Bits

Q0501

Counts per Timebase Register

AI002

Accumulator Registers: 16-Bit mode

AI006

32-Bit mode

AI006-007

Strobe Registers : 16-Bit mode
32-Bit mode

AI007
AI008-009

18.4.2

Type B Counter Operation

The  Type  B  counter  has  a  Strobe  register,  an  Accumulator  and  a  Counts-per-Timebase
register.  Except for the Counts per Timebase Register, these operate as described for Type
A counters.

For a B-type counter, the Counts per Timebase value represents the relative shift over the
sample time, not an exact number of counts. For example, if the counter starts at 10, counts
up to 20, and then counts back to 15, the resulting counts per timebase value is 5.

Figure 191

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Type B Counter Examples

Low Limit = 0

High Limit = 200

On Preset = 150

Off Preset = 160

Figure 192

Figure 193

Figure 194

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18.5

High-Speed Counter Outputs

Four high-speed outputs (three for a Nano PLC) can be individually configured as High-
Speed Counter outputs, PWM outputs, or Pulse Train outputs.

When the Counter Type configured is both Type A and Type B, PWM and Pulse Train outputs
1-3 are not available because A-QUAD-B counting uses output channels 1

–

3, as shown

earlier in this chapter.

If the configurations are changed for HSC, PWM, and Pulse outputs, the new outputs take
effect when the PLC changes from Stop to Run mode and the enable output bit is ON. When
the transition to Run mode occurs, the currently configured output stops running and the
new configuration takes over.

Results vary with temperature, but the maximums and minimums shown below apply
across the entire operating range for the unit (both temperature and DC output voltage).

18.5.1

Pulldown Resistor

For Micro -10, -14, -23 and -28 PLCs, a pulldown resistor, connected between the output
(Q1, 2, 3, or 4) and Common, is required for high frequency Pulse and PWM (up to 5kHz)
outputs and for duty cycles in the lower ranges (5% and lower).

A 1.5 kΩ,

0.5-watt resistor is

recommended.

Micro -20, -40, and -64 do not require a pulldown resistor.

18.5.2

Duty Cycle Limits: with 1.5k



pulldown resistor -

UDR005/006/010 & UAL004/005/006

Figure 195

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18.5.3

Duty Cycle Limits: with 1.5k



pulldown resistor -

UDD104/110 & NDD101

Figure 196

18.5.4

Counter Output Presets

Each counter output has a Preset on and off point. Both points must lie between the

counter’s configured high and low limits. Both the Presets and th

e High/Low limits are

initially set up as part of the PLC configuration. The Presets can be changed during operation
by using a COMMREQ function as explained later in this chapter.

The output state indicates when the Accumulator value is between the Preset on and off
points. For example, using the Type B counter:

Figure 197

If the output is enabled for the High-Speed Counter being used, the output turns on as
described in the Type A and Type B counter sections.

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The minimum span that should be configured between the On and Off Presets depends on
the count frequency.

For this Count Frequency:

Minimum Span Between On Preset and Off Preset
Should Be:

100kHz

100 counts

90kHz

90 counts

80kHz

80 counts

70kHz

70 counts

60kHZ

60 counts

50kHz

50 counts

40kHz

40 counts

30kHz

30 counts

25kHz

25 counts

20kHz

20 counts

15kHz

15 counts

10kHz

10 counts

5kHz

5 counts

2kHz

2 counts

1kHz

1 count

less than 1kHz

no gap required

Note:

Count frequencies above 10 kHz are supported only on 20-, 40-, and 64-point Micro PLCs.

18.6

PWM Outputs

Pulse Width-Modulated outputs can be used to control DC and stepper motors. Channels
are  set  up  for  PWM  output  operation  in  the  PLC  configuration  by  setting  the  Channel
Function  to  PWM.  If  a  channel  is  configured  as  a  PWM  output,  then  references  %I0001
through %I0008, which are normally reserved for High-Speed Counter inputs, can be used
as standard inputs in the application.

18.6.1

Enabling and Disabling a PWM Output

A PWM output is turned on from the application program by setting its Enable Output bit to
1. The output is turned off by setting its Enable Output bit to 0.

When a PWM output starts operating, it continues until a new configuration is received, a
store occurs (logic and/or configuration), a write to the user storage device occurs, or the
Output Enable bit is cleared. A PWM output stops if an invalid frequency or duty cycle value
is commanded.

If a PWM output is running when power is lost and the Output Enable bit remains set to 1,
the output starts again as soon as power is restored and the PLC transitions to Run mode.

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Channel 1

Channel 2

Channel 3

Channel 4

PWM Frequency

AQ002

AQ004

AQ006

AQ008

PWM Duty Cycle

AQ003

AQ005

AQ007

AQ009

Enable Output

Q0505

Q0506

Q0507

Q0508

18.6.2

PWM Frequency

The frequency of a PWM output (15Hz to 65kHz for Micro-20, -40, and -64 PLCs and 15Hz
to 5kHz for other models) is specified from the application program by writing a value (15
to 65000 for Micro-20, -40, -64 PLC or 15 to 5000 for other Micro PLCs) to the associated
frequency reference, as shown above. The actual frequency output can have a tolerance of
1%.

18.6.3

PWM Duty Cycle

The PWM duty cycle is set up by writing a value (0 to 10000) to the channel’s Duty Cycle

reference, as shown above. Both frequency and duty cycle can be changed while the output
is enabled. The minimum and maximum duty cycle values depend on the frequency.

18.6.4

Load Correction for PWM Outputs

The PLC optical isolators can skew the duty cycle, depending on temperature and load.  To
compensate for this, the Micro PLC automatically applies an additional load correction time
to the zero-output time of each pulse. The default load correction time is: 2µS for 20/40/64-
point Micro PLCs with DC outputs, 35µS  for other Micro PLCs with DC outputs, 10µS for
20/40/64-point  Micro  PLCs  with  relay  outputs,  or  85µS  for  other  Micro  PLCs  with  relay
outputs.

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