Полупроводники. Каталог (2011 год)

WT8045

Synchronous Signal Discriminator and

Power Saving Detector for Green Monitor



Weltrend Semiconductor, Inc.

2F., No. 24, Industry E. 9th Rd.

Science-Based Industrial Park

Hsin-Chu, Taiwan, R.O.C.

Tel: 886-35-780241

Fax: 886-35-770419

OSCin

HSin

OSCout

VSin

H_out

V_out

VDD

WT8045N28P2

F43.5K

F36.2K

PM3

PM1

Vss

QHRC

640x400
(31.5K/37.5K)

640x480(31.5K)

800x600(48K)

800x600(37.5K)

800x600(35.2K)

1024x768(56.5K)

1024x768 (I)

F33K

640x480(37.5K)

1024x768 (NI)

QV128

QVRC

F52K

PM2

OSCin

HSin

OSCout

VSin

H_out

V_out

VDD

WT8045N28P6

F43.5K

F36.2K

PM3

PM1

Vss

QHRC

640x400
(31.5K/37.5K)

640x480(31.5K)

800x600(48K)

800x600(37.5K)

800x600(35.2K)

1024x768(56.5K)

1024x768 (I)

F33K

640x480(37.5K)

1024x768 (NI)

QV1

QVRC

F52K

PM2

OSCin

HSin

OSCout

VSin

H_out

V_out

VDD

WT8045N28P7

F43.5K

F36.2K

PM3

PM1
+PM2

Vss

QHRC

640x400
(31.5K/37.5K)

640x480(31.5K)

800x600(48K)

800x600(37.5K)

800x600(35.2K)

1024x768(56.5K)

1024x768 (I)

F33K

640x480(37.5K)

1024x768 (NI)

QV128

QVRC

F52K

Mute

OSCin

HSin

OSCout

VSin

H_out

V_out

VDD

WT8045N28P8

F43.5K

F36.2K

PM3

PM1
+PM2

Vss

QHRC

640x400
(31.5K/37.5K)

640x480(31.5K)

800x600(48K)

800x600(37.5K)

800x600(35.2K)

1024x768(56.5K)

1024x768 (I)

F33K

640x480(37.5K)

1024x768 (NI)

QV1

QVRC

F52K

Mute

Note: The Hout and Vout pin of N28P2, N28P6, N28P7 and N28P8 are positive pulse.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

Microprocessor

Supervisory Circuits

ADM690–ADM695

FEATURES
Superior Upgrade for MAX690–MAX695
Specified Over Temperature
Low Power Consumption (5 mW)
Precision Voltage Monitor
Reset Assertion Down to 1 V V

Low Switch On-Resistance 1.5

Normal,

in Backup

High Current Drive (100 mA)
Watchdog Timer—100 ms, 1.6 s, or Adjustable
600 nA Standby Current
Automatic Battery Backup Power Switching
Extremely Fast Gating of Chip Enable Signals (5 ns)
Voltage Monitor for Power Fail

APPLICATIONS
Microprocessor Systems
Computers
Controllers
Intelligent Instruments
Automotive Systems

GENERAL DESCRIPTION
The ADM690–ADM695 family of supervisory circuits offers
complete single chip solutions for power supply monitoring and
battery control functions in microprocessor systems. These
functions include

P reset, backup battery switchover, watchdog

timer, CMOS RAM write protection, and power failure warn-
ing. The complete family provides a variety of configurations to
satisfy most microprocessor system requirements.

The ADM690, ADM692 and ADM694 are available in 8-pin
DIP packages and provide:

1. Power-on reset output during power-up, power-down and

brownout conditions. The

RESET

output remains opera-

tional with V

as low as 1 V.

2. Battery backup switching for CMOS RAM, CMOS

microprocessor or other low power logic.

3. A reset pulse if the optional watchdog timer has not been

toggled within a specified time.

4. A 1.3 V threshold detector for power fail warning, low battery

detection, or to monitor a power supply other than +5 V.

The ADM691, ADM693 and ADM695 are available in 16-pin
DIP and small outline packages and provide three additional
functions.

1. Write protection of CMOS RAM or EEPROM.

2. Adjustable reset and watchdog timeout periods.

3. Separate watchdog timeout, backup battery switchover, and

low V

status outputs.

The ADM690–ADM695 family is fabricated using an advanced
epitaxial CMOS process combining low power consumption
(5 mW), extremely fast Chip Enable gating (5 ns) and high reli-
ability.

RESET

assertion is guaranteed with V

as low as 1 V.

In addition, the power switching circuitry is designed for mini-
mal voltage drop thereby permitting increased output current
drive of up to 100 mA without the need for an external pass
transistor.

FUNCTIONAL BLOCK DIAGRAMS

4.65V

WATCHDOG

TRANSITION DETECTOR

1.3V

ADM691
ADM693
ADM695

OUT

BATT

WATCHDOG

INPUT (WDI)

POWER FAIL

INPUT (PFI)

VOLTAGE DETECTOR = 4.65V (ADM691, ADM695)

4.40V (ADM693)

POWER FAIL
OUTPUT (PFO)

RESET

WATCHDOG

TIMER

RESET &

WATCHDOG

TIMEBASE

RESET

GENERATOR

BATT ON

OSC IN

OSC SEL

WATCHDOG
OUTPUT (WDO)

RESET

LOW LINE

OUT

4.65V

RESET

GENERATOR

WATCHDOG

TRANSITION DETECTOR

(1.6s)

1.3V

ADM690
ADM692
ADM694

OUT

BATT

WATCHDOG

INPUT (WDI)

POWER FAIL

INPUT (PFI)

VOLTAGE DETECTOR = 4.65V (ADM690, ADM694)

4.40V (ADM692)

RESET PULSE WIDTH = 50ms (ADM690, ADM692)

200ms (ADM694)

POWER FAIL
OUTPUT (PFO)

RESET

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700

Fax: 617/326-8703

ADM690–ADM695–SPECIFICATIONS

Parameter

Min

Typ

Max

Units

Test Conditions/Comments

BATTERY BACKUP SWITCHING

Operating Voltage Range

ADM690, ADM691, ADM694, ADM695

4.75

5.5

ADM692, ADM693

4.5

5.5

BATT

Operating Voltage Range

ADM690, ADM691, ADM694, ADM695

2.0

4.25

ADM692, ADM693

2.0

4.0

OUT

Output Voltage

– 0.05

– 0.025

OUT

= 1 mA

– 0.5

– 0.25

OUT

≤

100 mA

OUT

in Battery Backup Mode

BATT

– 0.05 V

BATT

– 0.02

OUT

= 250

A, V

< V

BATT

– 0.2 V

Supply Current (Excludes I

OUT

)

1.95

OUT

= 100 mA

Supply Current in Battery Backup Mode

0.6

= 0 V, V

BATT

= 2.8 V

Battery Standby Current

5.5 V > V

> V

BATT

+ 0.2 V

(+ = Discharge, – = Charge)

–0.1

+0.02

= +25

–1.0

+0.02

Battery Switchover Threshold

Power Up

– V

BATT

Power Down

Battery Switchover Hysteresis

BATT ON Output Voltage

0.3

SINK

= 3.2 mA

BATT ON Output Short Circuit Current

BATT ON = V

OUT

= 4.5 V Sink Current

0.5

BATT ON = 0 V Source Current

RESET AND WATCHDOG TIMER

Reset Voltage Threshold

ADM690, ADM691, ADM694, ADM695

4.5

4.65

4.73

ADM692, ADM693

4.25

4.4

4.48

Reset Threshold Hysteresis

Reset Timeout Delay

ADM690, ADM691, ADM692, ADM693

OSC SEL = HIGH, V

= 5 V, T

= +25

ADM694, ADM695

140

200

280

OSC SEL = HIGH, V

= 5 V, T

= +25

Watchdog Timeout Period, Internal Oscillator

1.0

1.6

2.25

Long Period, V

= 5 V, T

= +25

100

140

Short Period, V

= 5 V, T

= +25

Watchdog Timeout Period, External Clock

3840

4097

Cycles

Long Period

768

1025

Cycles

Short Period

Minimum WDI Input Pulse Width

= 0.4, V

= 3.5 V

RESET

Output Voltage @ V

= +1 V

200

SINK

= 10

A, V

= 1 V

RESET

LOW

LINE

Output Voltage

0.4

SINK

= 1.6 mA, V

= 4.25 V

3.5

SOURCE

= 1

A, V

= 5 V

RESET

WDO

Output Voltage

0.4

SINK

= 1.6 mA, V

= 5 V

3.5

SOURCE

= 1

A, V

= 4.25 V

Output Short Circuit Source Current

Output Short Circuit Sink Current

WDI Input Threshold

= 5 V

Logic Low

0.8

Logic High

3.5

WDI Input Current

WDI = V

OUT

, T

= +25

–50

–15

WDI = 0 V, T

= +25

POWER FAIL DETECTOR

PFI Input Threshold

1.25

1.3

1.35

= +5 V

PFI Input Current

–25

0.01

+25

PFO

Output Voltage

0.4

SINK

= 3.2 mA

3.5

SOURCE

= 1

PFO

Short Circuit Source Current

PFI = Low,

PFO

= 0 V

PFO

Short Circuit Sink Current

PFI = High,

PFO

= V

OUT

CHIP ENABLE GATING

Threshold

0.8

3.0

Pull-Up Current

OUT

Output Voltage

0.4

SINK

= 3.2 mA

OUT

– 1.5

SOURCE

= 3.0 mA

OUT

– 0.05

SOURCE

= 1

A, V

= 0 V

Propagation Delay

REV. A

= Full Operating Range, V

BATT

= +2.8 V, T

= T

MIN

MAX

unless otherwise noted)

–2–

Parameter

Min

Typ

Max

Units

Test Conditions/Comments

OSCILLATOR

OSC IN Input Current

OSC SEL Input Pull-Up Current

OSC IN Frequency Range

250

kHz

OSC SEL = 0 V

OSC IN Frequency with External Capacitor

kHz

OSC SEL = 0 V, C

OSC

= 47 pF

NOTE

WDI is a three level input which is internally biased to 38% of V

and has an input impedance of approximately 125 k

Ω

Specifications subject to change without notice.

ADM690–ADM695

REV. A

–3–

ABSOLUTE MAXIMUM RATINGS*

= +25

C unless otherwise noted)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

BATT

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

All Other Inputs . . . . . . . . . . . . . . . . . . –0.3 V to V

OUT

+ 0.5 V

Input Current

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA

BATT

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Power Dissipation, N-8 DIP . . . . . . . . . . . . . . . . . . . . 400 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 120

C/W

Power Dissipation, Q-8 DIP . . . . . . . . . . . . . . . . . . . . 500 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 125

C/W

Power Dissipation, N-16 DIP . . . . . . . . . . . . . . . . . . . 600 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 135

C/W

Power Dissipation, Q-16 DIP . . . . . . . . . . . . . . . . . . . 600 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 100

C/W

Power Dissipation, R-16 SOIC . . . . . . . . . . . . . . . . . . 600 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 110

C/W

Operating Temperature Range

Industrial (A Version) . . . . . . . . . . . . . . . . . –40

C to +85

Extended (S Version) . . . . . . . . . . . . . . . . . –55

C to +125

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300

Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . +215

Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220

Storage Temperature Range . . . . . . . . . . . . . –65

C to +150

*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum ratings for extended periods of time may affect device reliability.

ORDERING GUIDE

Model

Temperature Range

Package Option

ADM690AN

–40

C to +85

N-8

ADM690AQ

–40

C to +85

Q-8

ADM690SQ

–55

C to +125

Q-8

ADM691AN

–40

C to +85

N-16

ADM691AR

–40

C to +85

R-16

ADM691AQ

–40

C to +85

Q-16

ADM691SQ

–55

C to +125

Q-16

ADM692AN

–40

C to +85

N-8

ADM692AQ

–40

C to +85

Q-8

ADM692SQ

–55

C to +125

Q-8

ADM693AN

–40

C to +85

N-16

ADM693AR

–40

C to +85

R-16

ADM693AQ

–40

C to +85

Q-16

ADM693SQ

–55

C to +125

Q-16

ADM694AN

–40

C to +85

N-8

ADM694AQ

–40

C to +85

Q-8

ADM694SQ

–55

C to +125

Q-8

ADM695AN

–40

C to +85

N-16

ADM695AR

–40

C to +85

R-16

ADM695AQ

–40

C to +85

Q-16

ADM695SQ

–55

C to +125

Q-16

WARNING!

ESD SENSITIVE DEVICE

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADM690–ADM695 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.

ADM690–ADM695

REV. A

–4–

PIN FUNCTION DESCRIPTION

Mnemonic

Function

Power Supply Input: +5 V Nominal.

BATT

Backup Battery Input. Connect to Ground if a backup battery is not used.

OUT

Output Voltage, V

or V

BATT

is internally switched to V

OUT

depending on which is at the highest potential. V

OUT

can supply up to 100 mA to power CMOS RAM. Connect V

OUT

to V

if V

OUT

and V

BATT

are not used.

GND

0 V. Ground reference for all signals.

RESET

Logic Output.

RESET

goes low if

1. V

falls below the Reset Threshold

2. V

falls below V

BATT

3. The watchdog timer is not serviced within its timeout period.

The reset threshold is typically 4.65 V for the ADM690/ADM691/ADM694/ADM695 and 4.4 V for the ADM692 and
ADM693.

RESET

remains low for 50 ms (ADM690/ADM691/ADM692/ADM693) or 200 ms (ADM694/ADM695)

after V

returns above the threshold.

RESET

also goes low for 50 (200) ms if the watchdog timer is enabled but not

serviced within its timeout period. The

RESET

pulse width can be adjusted on the ADM691/ADM693/ADM695 as

shown in Table I. The

RESET

output has an internal 3

A pull up, and can either connect to an open collector

Reset bus or directly drive a CMOS gate without an external pull-up resistor.

WDI

Watchdog Input. WDI is a three level input. If WDI remains either high or low for longer than the watchdog timeout
period,

RESET

pulses low and WDO goes low. The timer resets with each transition on the WDI line. The watchdog

timer may be disabled if WDI is left floating or is driven to midsupply.

PFI

Power Fail Input. PFI is the noninverting input to the Power Fail Comparator when PFI is less than 1.3 V,

PFO

goes low. Connect PFI to GND or V

OUT

when not used.

PFO

Power Fail Output.

PFO

is the output of the Power Fail Comparator. It goes low when PFI is less than 1.3 V. The

comparator is turned off and

PFO

goes low when V

is below V

BATT

Logic Input. The input to the

gating circuit. Connect to GND or V

OUT

if not used.

OUT

Logic Output.

OUT

is a gated version of the

signal.

OUT

tracks

when V

is above the reset

threshold. If V

is below the reset threshold,

OUT

is forced high. See Figures 5 and 6.

BATT ON

Logic Output. BATT ON goes high when V

OUT

is internally switched to the V

BATT

input. It goes low when V

OUT

is internally switched to V

. The output typically sinks 35 mA and can directly drive the base of an external

PNP transistor to increase the output current above the 100 mA rating of V

OUT

LOW LINE

Logic Output.

LOW LINE

goes low when V

falls below the reset threshold. It returns high as soon as V

rises

above the reset threshold.

RESET

Logic Output. RESET is an active high output. It is the inverse of

RESET

OSC SEL

Logic Oscillator Select Input. When OSC SEL is unconnected (floating) or driven high, the internal oscillator sets
the reset active time and watchdog timeout period. When OSC SEL is low, the external oscillator input, OSC IN,
is enabled. OSC SEL has a 3

A internal pull up, (see Table I).

OSC IN

Oscillator Logic Input. With OSC SEL low, OSC IN can be driven by an external clock signal or an external
capacitor can be connected between OSC IN and GND. This sets both the reset active pulse timing and the watch-
dog timeout period (see Table I and Figure 4). With OSC SEL high or floating, the internal oscillator is enabled
and the reset active time is fixed at 50 ms typ. (ADM691/ADM693) or 200 ms typ (ADM695). In this mode the
OSC IN pin selects between fast (100 ms) and slow (1.6 s) watchdog timeout periods. In both modes, the timeout
period immediately after a reset is 1.6 s typical.

WDO

Logic Output. The Watchdog Output,

WDO

, goes low if WDI remains either high or low for longer than the

watchdog timeout period.

WDO

is set high by the next transition at WDI. If WDI is unconnected or at midsupply,

the watchdog timer is disabled and

WDO

remains high.

WDO

also goes high when

LOW LINE

goes low.

ADM690–ADM695

REV. A

–5–

PIN CONFIGURATIONS

PRODUCT SELECTION GUIDE

Part

Nominal Reset

Nominal V

Nominal Watchdog

Battery Backup

Base Drive

Chip Enable

Number

Time

Reset Threshold

Timeout Period

Switching

Ext PNP

Signals

ADM690

50 ms

4.65 V

1.6 s

Yes

ADM691

50 ms or ADJ

4.65 V

100 ms, 1.6 s, ADJ

Yes

ADM692

50 ms

4.4 V

1.6 s

Yes

ADM693

50 ms or ADJ

4.4 V

100 ms, 1.6 s, ADJ

Yes

ADM694

200 ms

4.65 V

1.6 s

Yes

ADM695

200 ms or ADJ

4.65 V

100 ms, 1.6 s, ADJ

Yes

CIRCUIT INFORMATION
Battery Switchover Section
The battery switchover circuit compares V

to the V

BATT

input, and connects V

OUT

to whichever is higher. Switchover

occurs when V

is 50 mV higher than V

BATT

as V

falls, and

when V

is 70 mV greater than V

BATT

as V

rises. This

20 mV of hysteresis prevents repeated rapid switching if V

falls very slowly or remains nearly equal to the battery voltage.

Figure 1. Battery Switchover Schematic

During normal operation with V

higher than V

BATT

, V

is in-

ternally switched to V

OUT

via an internal PMOS transistor

switch. This switch has a typical on-resistance of 1.5

Ω

and can

supply up to 100 mA at the V

OUT

terminal. V

OUT

is normally

used to drive a RAM memory bank which may require instanta-
neous currents of greater than 100 mA. If this is the case then a
bypass capacitor should be connected to V

OUT

. The capacitor

will provide the peak current transients to the RAM. A capaci-
tance value of 0.1

F or greater may be used.

If the continuous output current requirement at V

OUT

exceeds

100 mA or if a lower V

–V

OUT

voltage differential is desired,

an external PNP pass transistor may be connected in parallel
with the internal transistor. The BATT ON output (ADM691/
ADM693/ADM695) can directly drive the base of the external
transistor.

A 20

Ω

MOSFET switch connects the V

BATT

input to V

OUT

during battery backup. This MOSFET has very low input-to-
output differential (dropout voltage) at the low current levels
required for battery back up of CMOS RAM or other low
power CMOS circuitry. The supply current in battery back up
is typically 0.6

The ADM690/ADM691/ADM694/ADM695 operates with
battery voltages from 2.0 V to 4.25 V and the ADM692/ADM693
operates with battery voltages from 2.0 V to 4.0 V. High value
capacitors, either standard electrolytic or the farad size double
layer capacitors, can also be used for short-term memory back
up. A small charging current of typically 10 nA (0.1

A max)

flows out of the V

BATT

terminal. This current is useful for

maintaining rechargeable batteries in a fully charged condition.
This extends the life of the back up battery by compensating
for its self discharge current. Also note that this current poses
no problem when lithium batteries are used for back up since
the maximum charging current (0.1

A) is safe for even the

smallest lithium cells.

If the battery-switchover section is not used, V

BATT

should be

connected to GND and V

OUT

should be connected to V

TOP VIEW

(Not to Scale)

ADM691
ADM693
ADM695

GND

BATT

OUT

PFI

PFO

WDO

RESET

BATT ON

LOW LINE

OSC IN

OSC SEL

RESET

OUT

WDI

GND

BATT

OUT

PFI

PFO

WDI

RESET

TOP VIEW

(Not to Scale)

ADM690
ADM692
ADM694

ADM690–ADM695

REV. A

–6–

POWER FAIL

RESET

OUTPUT

RESET

is an active low output which provides a

RESET

signal

to the Microprocessor whenever V

is at an invalid level. When

falls below the reset threshold, the

RESET

output is forced

low. The nominal reset voltage threshold is 4.65 V (ADM690/
ADM691/ADM694/ADM695) or 4.4 V (ADM692/ADM693).

= RESET TIME.

V1 = RESET VOLTAGE THRESHOLD LOW

V2 = RESET VOLTAGE THRESHOLD HIGH

HYSTERESIS = V2–V1

LOW LINE

RESET

Figure 2. Power Fail Reset Timing

On power-up

RESET

will remain low for 50 ms (200 ms for

ADM694 and ADM695) after V

rises above the appropriate

reset threshold. This allows time for the power supply and mi-
croprocessor to stabilize. On power-down, the

RESET

output

remains low with V

as low as 1 V. This ensures that the

microprocessor is held in a stable shutdown condition.

This

RESET

active time is adjustable on the ADM691/ADM693/

ADM695 by using an external oscillator or by connecting an
external capacitor to the OSC IN pin. Refer to Table I and
Figure 4.

The guaranteed minimum and maximum thresholds of the
ADM690/ADM691/ADM694/ADM695 are 4.5 V and 4.73 V,
while the guaranteed thresholds of the ADM692/ADM693 are
4.25 V and 4.48 V. The ADM690/ADM691/ADM694/ADM695
is, therefore, compatible with 5 V supplies with a +10%, –5%
tolerance while the ADM692/ADM693 is compatible with 5 V

10% supplies. The reset threshold comparator has approxi-

mately 50 mV of hysteresis. The response time of the reset volt-
age comparator is less than 1

s. If glitches are present on the

line which could cause spurious reset pulses, then V

should be decoupled close to the device.

In addition to

RESET

the ADM691/ADM693/ADM695 con-

tain an active high

RESET

output. This is the complement of

RESET

and is intended for processors requiring an active high

RESET signal.

Watchdog Timer

RESET

The watchdog timer circuit monitors the activity of the micro-
processor in order to check that it is not stalled in an indefinite
loop. An output line on the processor is used to toggle the
Watchdog Input (WDI) line. If this line is not toggled within the
selected timeout period, a

RESET

pulse is generated. The

nominal watchdog timeout period is preset at 1.6 seconds on the
ADM690/ADM692/ADM694. The ADM691/ADM693/ADM695
may be configured for either a fixed “short” 100 ms or a “long”
1.6 second timeout period or for an adjustable timeout period.
If the “short” period is selected, some systems may be unable to
service the watchdog timer immediately after a reset, so the
ADM691/ADM693/ADM695 automatically selects the “long”
timeout period directly after a reset is issued. The watchdog
timer is restarted at the end of reset, whether the reset was
caused by lack of activity on WDI or by V

falling below the

reset threshold.

The normal (short) timeout period becomes effective following
the first transition of WDI after

RESET

has gone inactive. The

watchdog timeout period restarts with each transition on the
WDI pin. To ensure that the watchdog timer does not time out,
either a high-to-low or low-to-high transition on the WDI pin
must occur at or less than the minimum timeout period. If WDI
remains permanently either high or low, reset pulses will be
issued after each “long” timeout period (1.6 s). The watchdog
monitor can be deactivated by floating the Watchdog Input
(WDI) or by connecting it to midsupply.

RESET

WDO

WDI

= RESET TIME.

= NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD.

= WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET.

Figure 3. Watchdog Timeout Period and Reset Active
Time

ADM690–ADM695

REV. A

–7–

Table I. ADM691, ADM693, ADM695 Reset Pulse Width and Watchdog Timeout Selections

Watchdog Timeout Period

Reset Active Period

Immediately

OSC SEL

OSC IN

Normal

After Reset

ADM691/ADM693

ADM695

Low

External Clock Input

1024 CLKS

4096 CLKS

512 CLKS

2048 CLKS

Low

External Capacitor

260 ms

C/47 pF

1.04 s

C/47 pF

130 ms

C/47 pF

520 ms

C/47 pF

Floating or High

Low

100 ms

1.6 s

50 ms

200 ms

Floating or High

1.6 s

50 ms

200 ms

NOTE
With the OSC SEL pin low, OSC IN can be driven by an external clock signal, or an external capacitor can be connected between OSC IN and GND. The nominal
internal oscillator frequency is 10.24 kHz. The nominal oscillator frequency with external capacitor is: F

OSC

(Hz) = 184,001/C (pF).

The watchdog timeout period is fixed at 1.6 seconds, and the
reset pulse width is fixed at 50 ms on the ADM690/ADM692.
On the ADM694 the watchdog timeout period is also 1.6 sec-
onds but the reset pulse width is fixed at 200 ms. The ADM691/
ADM693/ADM695 allow these times to be adjusted as shown
in Table I. Figure 4 shows the various oscillator configurations
which can be used to adjust the reset pulse width and watchdog
timeout period.

The internal oscillator is enabled when OSC SEL is high or
floating. In this mode, OSC IN selects between the 1.6 second
and 100 ms watchdog timeout periods. With OSC IN connected
high or floating, the 1.6 second timeout period is selected; while
with it connected low, the 100 ms timeout period is selected. In
either case, immediately after a reset, the timeout period is 1.6
seconds. This gives the microprocessor time to reinitialize the
system. If OSC IN is low, then the 100 ms watchdog period be-
comes effective after the first transition of WDI. The software
should be written such that the I/O port driving WDI is left in
its power-up reset state until the initialization routines are com-
pleted and the microprocessor is able to toggle WDI at the mini-
mum watchdog timeout period of 70 ms.

Watchdog Output (WDO)
The Watchdog Output

WDO

(ADM691/ADM693/ADM695)

provides a status output which goes low if the watchdog timer
“times out” and remains low until set high by the next transition
on the Watchdog Input.

WDO

is also set high when V

goes

below the reset threshold.

OSC IN

OSC SEL

ADM691
ADM693
ADM695

CLOCK

0 TO 250kHz

Figure 4a. External Clock Source

OSC IN

OSC SEL

ADM691
ADM693
ADM695

OSC

Figure 4b. External Capacitor

OSC IN

OSC SEL

ADM691
ADM693
ADM695

Figure 4c. Internal Oscillator (1.6 Second Watchdog)

OSC IN

OSC SEL

ADM691
ADM693
ADM695

Figure 4d. Internal Oscillator (100 ms Watchdog)

ADM690–ADM695

REV. A

–8–

Gating and RAM Write Protection (ADM691/ADM693/

ADM695)
The ADM691/ADM693/ADM695 products include memory
protection circuitry which ensures the integrity of data in mem-
ory by preventing write operations when V

is at an invalid

level. There are two additional pins,

and

OUT

, which

may be used to control the Chip Enable or Write inputs of
CMOS RAM. When V

is present,

OUT

is a buffered replica

, with a 5 ns propagation delay. When V

falls below

the reset voltage threshold or V

BATT

, an internal gate forces

OUT

high, independent of

OUT

typically drives the

, or write input of battery

backed up CMOS RAM. This ensures the integrity of the data
in memory by preventing write operations when V

is at an in-

valid level. Similar protection of EEPROMs can be achieved by
using the

OUT

to drive the store or write inputs.

If the 5 ns typical propagation delay of

OUT

is excessive, con-

nect

to GND and use the resulting

OUT

to control a

high speed external logic gate.

ADM69x

OUT

LOW = 0

OK = 1

Figure 5. Chip Enable Gating

Power Fail Warning Comparator
An additional comparator is provided for early warning of failure
in the microprocessor’s power supply. The Power Fail Input
(PFI) is compared to an internal +1.3 V reference. The Power
Fail Output (

PFO

) goes low when the voltage at PFI is less than

1.3 V. Typically PFI is driven by an external voltage divider
which senses either the unregulated dc input to the system’s 5 V
regulator or the regulated 5 V output. The voltage divider ratio
can be chosen such that the voltage at PFI falls below 1.3 V sev-
eral milliseconds before the +5 V power supply falls below the
reset threshold.

PFO

is normally used to interrupt the micropro-

cessor so that data can be stored in RAM and the shut down
procedure executed before power is lost

ADM69x

POWER

FAIL

INPUT

POWER

1.3V

PFO

POWER
FAIL
OUTPUT

Figure 7. Power Fail Comparator

Table II. Input and Output Status In Battery Backup Mode

Signal

Status

OUT

is connected to V

BATT

via an internal

PMOS switch.

RESET

Logic low.

RESET

Logic high. The open circuit output voltage is
equal to V

OUT

LOW LINE

Logic low.

BATT ON

Logic high. The open circuit voltage is equal to
V

OUT.

WDI

WDI is ignored. It is internally disconnected
from the internal pull-up resistor and does not
source or sink current as long as its input voltage
is between GND and V

OUT

. The input voltage

does not affect supply current.

WDO

Logic high. The open circuit voltage is equal
to V

OUT

PFI

The Power Fail Comparator is turned off and
has no effect on the Power Fail Output.

PFO

Logic low.

is ignored. It is internally disconnected

from its internal pull-up and does not source or
sink current as long as its input voltage is
between GND and V

OUT

. The input voltage

does not affect supply current.

OUT

Logic high. The open circuit voltage is equal to
V

OUT

OSC IN

OSC IN is ignored.

OSC SEL

OSC SEL is ignored.

= RESET TIME.

V1 = RESET VOLTAGE THRESHOLD LOW

V2 = RESET VOLTAGE THRESHOLD HIGH

HYSTERESIS = V2–V1

LOW LINE

RESET

OUT

Figure 6. Chip Enable Timing

Typical Performance Curves–ADM690–ADM695

5.00

4.80

100

4.95

4.85

4.90

= 5V

= +25

SLOPE = 1.5

Ω

OUT

– V

OUT

– mA

Figure 8. V

OUT

vs. I

OUT

Normal

Operation

1.303

1.299

120

1.302

1.300

1.301

100

PFI INPUT THRESHOLD – V

TEMPERATURE –

Figure 11. PFI Input Threshold vs.
Temperature

1.25

0.8

0.5 0.6

0.3 0.4

0.7

0.2

0.1

PFI

1.3V

30pF

PFO

= 5V

= +25

1.35

TIME –

Figure 14. Power Fail Comparator
Response Time

2.80

2.76

1000

2.79

2.77

200

2.78

800

600

400

OUT

–

OUT

– V

SLOPE = 20

Ω

= 0V

BATT

= +2.8V

= +25

Figure 9. V

OUT

vs. I

OUT

Battery

Backup

120

100

= +5V

TEMPERATURE –

RESET ACTIVE TIME – ms

ADM690
ADM691
ADM692
ADM693

Figure 12. Reset Active Time vs.
Temperature

1.25

1.35

50 60

30 40

PFI

1.3V

30pF

PFO

= 5V

= +25

TIME –

Figure 15. Power Fail Comparator
Response Time

100

3.36 V

500ms

Figure 10. Reset Output Voltage vs.
Supply Voltage

4.70

4.62

120

4.68

4.64

4.66

100

TEMPERATURE –

RESET VOLTAGE THRESHOLD – V

= +5V

POWER-UP

POWER-DOWN

ADM690
ADM691
ADM694
ADM695

Figure 13. Reset Voltage Threshold
vs. Temperature

1.8

1.25

1.35

1.6

1.0 1.2

0.6 0.8

1.4

0.4

0.2

= 5V

= +25

PFI

1.3V

30pF

PFO

+5V

10k

+5V

TIME –

Figure 16. Power Fail Comparator
Response Time with Pull-Up Resistor

REV. A

–9–

ADM690–ADM695

REV. A

–10–

+APPLICATION INFORMATION
Increasing the Drive Current
If the continuous output current requirements at V

OUT

exceed

100 mA or if a lower V

–V

OUT

voltage differential is desired,

an external PNP pass transistor may be connected in parallel
with the internal transistor. The BATT ON output (ADM691/
ADM693/ADM695) can directly drive the base of the external
transistor.

OUT

BATTERY

+5V

INPUT

POWER

0.1

BATT

PNP TRANSISTOR

ADM691
ADM693
ADM695

Figure 17. Increasing the Drive Current

Using a Rechargeable Battery for Back Up
If a capacitor or a rechargeable battery is used for back up then
the charging resistor should be connected to V

OUT

since this

eliminates the discharge path that would exist during power
down if the resistor is connected to V

OUT

RECHARGEABLE

BATTERY

+5V

INPUT

POWER

0.1

BATT

ADM69x

I =

OUT

– V

BATT

Figure 18. Rechargeable Battery

Adding Hysteresis to the Power Fail Comparator
For increased noise immunity, hysteresis may be added to the
power fail comparator. Since the comparator circuit is nonin-
verting, hysteresis can be added simply by connecting a resistor be-
tween the

PFO

output and the PFI input as shown in Figure 19.

When

PFO

is low, resistor R

sinks current from the summing

junction at the PFI pin. When

PFO

is high, the series combina-

tion of R

and R

source current into the PFI summing junc-

tion. This results in differing trip levels for the comparator.

ADM69x

1.3V

PFO

7805

+7V TO +15V

INPUT

POWER

+5V

PFI

P NMI

PFO

= 1.3V

(

1+ ––– + –––

)

= 1.3V

(

1+ ––– – –––––––––––––

)

ASSUMING R

< <

THEN

HYSTERESIS V

– V

= 5V

(

–––

)

(5V – 1.3V)

1.3V (R

3 +

)

Figure 19. Adding Hysteresis to the Power Fail Comparator

Monitoring the Status of the Battery
The power fail comparator can be used to monitor the status of
the backup battery instead of the power supply if desired. This
is shown in Figure 20. The PFI input samples the battery volt-
age and generates an active low

PFO

signal when the battery

voltage drops below a chosen threshold. It may be necessary to
apply a test load in order to determine the loaded battery volt-
age. This can be done under processor control using

OUT.

Since

OUT

is forced high during the battery backup mode, the

test load will not be applied to the battery while it is in use, even
if the microprocessor is not powered.

ADM690–ADM695

REV. A

–11–

ADM69x

PFO

PFI

FROM

P I/O PIN

APPLIES TEST LOAD

TO BATTERY

LOW BATTERY

SIGNAL TO

P I/O PIN

+5V INPUT
POWER

BATT

OUT

BATTERY

20k

Ω

OPTIONAL

TEST LOAD

10M

Ω

10M

Ω

Figure 20. Monitoring the Battery Status

Alternate Watchdog Input Drive Circuits
The watchdog feature can be enabled and disabled under pro-
gram control by driving WDI with a 3-state buffer (Figure 21a).
When three-stated, the WDI input will float thereby disabling
the watchdog timer.

WDI

ADM69x

WATCHDOG
STROBE

CONTROL
INPUT

Figure 21a. Programming the Watchdog Input

This circuit is not entirely foolproof, and it is possible that a
software fault could erroneously 3-state the buffer. This would
then prevent the ADM69x from detecting that the microproces-
sor is no longer operating correctly. In most cases a better
method is to extend the watchdog period rather than disabling
the watchdog. This may be done under program control using
the circuit shown in Figure 21b. When the control input is high,
the OSC SEL pin is low and the watchdog timeout is set by the
external capacitor. A 0.01

F capacitor sets a watchdog timeout

delay of 100 seconds. When the control input is low, the OSC
SEL pin is driven high, selecting the internal oscillator. The
100 ms or the 1.6 s period is chosen, depending on which diode
in Figure 21b is used. With D1 inserted the internal timeout is
set at 100 ms, while with D2 inserted the timeout is set at 1.6 s.

OSC IN

OSC SEL

ADM69x

CONTROL
INPUT*

*LOW = INTERNAL TIMEOUT
HIGH = EXTERNAL TIMEOUT

Figure 21b. Programming the Watchdog Input

Replacing the Backup Battery
When changing the backup battery with system power on, spuri-
ous resets can occur when the battery is removed. This occurs
because the leakage current flowing out of the V

BATT

pin will

charge up the stray capacitance. If the voltage on V

BATT

reaches

within 50 mV of V

, a reset pulse is generated.

If spurious resets during battery replacement are acceptable,
then no action is required. If not, then one of the following
solutions should be considered:

1. A capacitor from V

BATT

to GND. This gives time while the

capacitor is charging up to replace the battery. The leakage
current will charge up the external capacitor towards the V

level. The time taken is related to the charging current, the
size of external capacitor and the voltage differential between
the capacitor and the charging voltage supply.

t = C

EXT

DIFF

The maximum leakage (charging) current is 1

A over tem-

perature and V

DIFF

= V

–V

BATT

. Therefore, the capacitor

size should be chosen such that sufficient time is available to
make the battery replacement.

EXT

= T

REQD

A/(V

–V

BATT

))

If a replacement time of 5 seconds is allowed and assuming a
V

of 4.5 V and a V

BATT

of 3 V

EXT

= 3.33

ADM69x

BATT

BATTERY

EXT

Figure 22a. Preventing Spurious RESETS During
Battery Replacement

2. A resistor from V

BATT

to GND. This will prevent the voltage

on V

BATT

from rising to within 50 mV of V

during battery

replacement.

ADM690–ADM695

REV. A

–12–

ADM690
ADM692
ADM694

PFO

+5V

CMOS RAM

POWER

I/O LINE

P NMI

P RESET

P SYSTEM

P POWER

OUT

RESET

WDI

GND

PFI

BATT

BATTERY

0.1

Figure 23a. ADM690/ADM692/ADM694 Typical Application
Circuit A

Figure 23b shows a similar application but in this case the PFI
input monitors the unregulated input to the 7805 voltage regu-
lator. This gives an earlier warning of an impending power fail-
ure. It is useful with processors operating at low speeds or

where there are a significant number of housekeeping tasks to be
completed before the power is lost.

ADM690
ADM692
ADM694

PFO

7805

INPUT

POWER

V > 8V

+5V

CMOS RAM

POWER

I/O LINE

P NMI

P RESET

P SYSTEM

P POWER

OUT

RESET

WDI

GND

PFI

BATT

0.1

BATTERY

0.1

Figure 23b. ADM690/ADM692/ADM694 Typical Application
Circuit B

ADM691, ADM693, ADM695
A typical connection for the ADM691/ADM693/ADM695 is
shown in Figure 24. CMOS RAM is powered from V

OUT

. When

5 V power is present this is routed to V

OUT

. If V

fails then

BATT

is routed to V

OUT

. V

OUT

can supply up to 100 mA from

, but if more current is required, an external PNP transistor

can be added. When V

is higher than V

BATT

, the BATT ON

output goes low, providing up to 25 mA of base drive for the
external transistor. A 0.1

F capacitor is connected to V

OUT

supply the transient currents for CMOS RAM. When V

lower than V

BATT

, an internal 20

Ω

MOSFET connects the

backup battery to V

OUT

R =(V

– 50 mV)/1

Note that the resistor will discharge the battery slightly. With a
V

supply of 4.5 V, a suitable resistor is 4.3 M

Ω

. With a 3 V

battery this will draw around 700 nA. This will be negligible in
most cases.

ADM69x

BATT

BATTERY

Figure 22b. Preventing Spurious RESETS During Battery
Replacement

TYPICAL APPLICATIONS
ADM690, ADM692 AND ADM694
Figure 23 shows the ADM690/ADM692/ADM694 in a typical
power monitoring, battery backup application. V

OUT

powers the

CMOS RAM. Under normal operating conditions with V

present, V

OUT

is internally connected to V

. If a power failure

occurs, V

will decay and V

OUT

will be switched to V

BATT

thereby maintaining power for the CMOS RAM. A

RESET

pulse is also generated when V

falls below 4.65 V for the

ADM690/ADM694 or 4.4 V for the ADM692.

RESET

will

remain low for 50 ms (200 ms for ADM694) after V

returns

to 5 V.

The watchdog timer input (WDI) monitors an I/O line from the

P system. This line must be toggled once every 1.6 seconds to

verify correct software execution. Failure to toggle the line indi-
cates that the

P system is not correctly executing its program

and may be tied up in an endless loop. If this happens, a reset
pulse is generated to initialize the processor.

If the watchdog timer is not needed, the WDI input should be
left floating.

The Power Fail Input, PFI, monitors the input power supply via
a resistive divider network. The voltage on the PFI input is com-
pared with a precision 1.3 V internal reference. If the input volt-
age drops below 1.3 V, a power fail output (

PFO

) signal is

generated. This warns of an impending power failure and may
be used to interrupt the processor so that the system may be
shut down in an orderly fashion. The resistors in the sensing
network are ratioed to give the desired power fail threshold
voltage V

= (1.3 R

) + 1.3 V

= (V

/1.3) – 1

ADM690–ADM695

REV. A

–13–

ADM691
ADM693
ADM695

PFO

INPUT POWER
+5V

OUT

WDI

GND

PFI

BATT

0.1

BATTERY

RESET

0.1

OSC IN

OSC SEL

LOW LINE

WDO

SYSTEM STATUS

INDICATORS

CMOS

RAM

ADDRESS

DECODE

I/O LINE

NMI

RESET

A0–A15

0.1

RESET

OUT

BATT

Figure 24. ADM691/ADM693/ADM695 Typical Application

Reset Output
The internal voltage detector monitors V

and generates a

RESET

output to hold the microprocessor’s Reset line low

when V

is below 4.65 V (4.4 V for ADM693). An internal

timer holds

RESET

low for 50 ms (200 ms for the ADM695)

after V

rises above 4.65 V (4.4 V for ADM693). This prevents

repeated toggling of

RESET

even if the 5 V power drops out

and recovers with each power line cycle.

The crystal oscillator normally used to generate the clock for mi-
croprocessors can take several milliseconds to stabilize. Since
most microprocessors need several clock cycles to reset,

RESET

must be held low until the microprocessor clock oscillator has
started. The power-up

RESET

pulse lasts 50 ms (200 ms for the

ADM695) to allow for this oscillator start-up time. If a different
reset pulse width is required, then a capacitor should be con-
nected to OSC IN or an external clock may be used. Please refer
to Table I and Figure 4. The manual reset switch and the 0.1

capacitor connected to the reset line can be omitted if a manual
reset is not needed. An inverted, active high, RESET output is
also available.

Power Fail Detector
The +5 V V

power line is monitored via a resistive potential

divider connected to the Power Fail Input (PFI). When the
voltage at PFI falls below 1.3 V, the Power Fail Output (

PFO

)

drives the processor’s NMI input low. If for example a Power
Fail threshold of 4.8 V is set with resistors R

and R

, the micro-

processor will have the time when V

falls from 4.8 V to 4.65 V

to save data into RAM. An earlier power fail warning can be
generated if the unregulated dc input to the 5 V regulator is
available for monitoring. This will allow more time for micro-
processor housekeeping tasks to be completed before power is
lost.

RAM Write Protection
The ADM691/ADM693/ADM695

OUT

line drives the Chip

Select inputs of the CMOS RAM.

OUT

follows

as long

as V

is above the 4.65 V (4.4 V for ADM693) reset threshold.

If V

falls below the reset threshold,

OUT

goes high, inde-

pendent of the logic level at

. This prevents the micropro-

cessor from writing erroneous data into RAM during power-up,
power-down, brownouts and momentary power interruptions.

Watchdog Timer
The microprocessor drives the Watchdog Input (WDI) with an
I/O line. When OSC IN and OSC SEL are unconnected, the
microprocessor must toggle the WDI pin once every 1.6 sec-
onds to verify proper software execution. If a hardware or soft-
ware failure occurs such that WDI not toggled, the ADM691/
ADM693 will issue a 50 ms (200 ms for ADM695)

RESET

pulse after 1.6 seconds. This typically restarts the micro-
processor’s power-up routine. A new

RESET

pulse is issued

every 1.6 seconds until WDI is again strobed. If a different
watchdog timeout period is required, then a capacitor should be
connected to OSC IN or an external clock may be used. Please
refer to Table I and Figure 4.

The WATCHDOG OUTPUT (

WDO

) goes low if the watch-

dog timer is not serviced within its timeout period. Once

WDO

goes low, it remains low until a transition occurs at WDI. The
watchdog timer feature can be disabled by leaving WDI
unconnected.

The

RESET

output has an internal 3

A pull-up, and can either

connect to an open collector reset bus or directly drive a CMOS
gate without an external pull-up resistor.

ADM690–ADM695

REV. A

–14–

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

8-Pin Plastic DIP (N-8)

PIN 1

0.280 (7.11)

0.240 (6.10)

SEATING
PLANE

0.060 (1.52)

0.015 (0.38)

0.150
(3.81)
MIN

0.210

(5.33)

MAX

0.160 (4.06)

0.115 (2.93)

0.430 (10.92)

0.348 (8.84)

0.022 (0.558)

0.014 (0.356)

0.070 (1.77)

0.045 (1.15)

0.100
(2.54)

BSC

0.325 (8.25)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

0.195 (4.95)

0.115 (2.93)

16-Lead Plastic DIP (N-16)

0.840 (21.33)
0.745 (18.93)

0.325 (8.25)
0.300 (7.62)

0.015 (0.381)
0.008 (0.204)

0.195 (4.95)
0.115 (2.93)

PIN 1

0.280 (7.11)
0.240 (6.10)

0.210

(5.33)

0.200 (5.05)
0.125 (3.18)

0.022 (0.558)
0.014 (0.356)

0.100
(2.54)

BSC

SEATING
PLANE

0.060 (1.52)
0.015 (0.38)

0.150
(3.81)

0.070 (1.77)
0.045 (1.15)

8-Pin Cerdip (Q-8)

PIN 1

0.420 (10.67)

MAX

0.060 (1.52)

0.015 (0.38)

0.015 (0.381)

0.008 (0.204)

0.150
(3.81)
MIN

0.310 (7.87)

0.220 (5.59)

0.320 (8.13)

0.290 (7.37)

0.200
(5.08)

MAX

PLANE

SEATING

0.070 (1.78)

0.30 (0.76)

0.100 (2.54)

BSC

0.022 (0.558)

0.014 (0.356)

Полупроводники. Каталог (2011 год) - часть 12