содержание .. 3 4 5 6 ..
Полупроводники. Каталог (2011 год) - часть 5
last byte. At the end of the last received byte, a not
acknowledge is returned.
The master device generates all the serial clock pulses
and the START and STOP conditions. A transfer
is ended with a STOP condition or with a repeated
START condition. Since a repeated START condition
is also the beginning of the next serial transfer, the bus
will not be released. Data is transferred with the most
significant bit (MSB) first.
The DS3231 can operate in the following two modes:
Slave receiver mode (DS3231 write mode):
Serial
data and clock are received through SDA and SCL.
After each byte is received, an acknowledge bit is
transmitted. START and STOP conditions are recog-
nized as the beginning and end of a serial transfer.
Address recognition is performed by hardware after
reception of the slave address and direction bit. The
slave address byte is the first byte received after the
master generates the START condition. The slave
address byte contains the 7-bit DS3231 address,
which is 1101000, followed by the direction bit (R/
W
),
which is 0 for a write. After receiving and decoding the
slave address byte, the DS3231 outputs an acknowl-
edge on SDA. After the DS3231 acknowledges the
slave address + write bit, the master transmits a word
address to the DS3231. This sets the register pointer
on the DS3231, with the DS3231 acknowledging the
transfer. The master may then transmit zero or more
bytes of data, with the DS3231 acknowledging each
byte received. The register pointer increments after
each data byte is transferred. The master generates a
STOP condition to terminate the data write.
Slave transmitter mode (DS3231 read mode):
The
first byte is received and handled as in the slave
receiver mode. However, in this mode, the direction
bit indicates that the transfer direction is reversed.
Serial data is transmitted on SDA by the DS3231 while
the serial clock is input on SCL. START and STOP
conditions are recognized as the beginning and end
of a serial transfer. Address recognition is performed
by hardware after reception of the slave address and
direction bit. The slave address byte is the first byte
received after the master generates a START condi-
tion. The slave address byte contains the 7-bit DS3231
address, which is 1101000, followed by the direction
bit (R/
W
), which is 1 for a read. After receiving and
decoding the slave address byte, the DS3231 outputs
an acknowledge on SDA. The DS3231 then begins to
transmit data starting with the register address pointed
to by the register pointer. If the register pointer is not
written to before the initiation of a read mode, the first
address that is read is the last one stored in the regis-
ter pointer. The DS3231 must receive a not acknowl-
edge to end a read.
Figure 5. Data Write/Read (Write Pointer, Then Read)—Slave Receive and Transmit
S - START
Sr - REPEATED START
A - ACKNOWLEDGE (ACK)
P - STOP
A
- NOT ACKNOWLEDGE (NACK)
R/
W
- READ/WRITE OR DIRECTION BIT ADDRESS
<R/
W
>
<WORD ADDRESS (n)> <SLAVE ADDRESS (n)>
<SLAVE
ADDRESS>
<R/
W
>
A
XXXXXXXX
A
1101000
1101000
S
Sr
0
A
1
DATA TRANSFERRED
(X + 1 BYTES + ACKNOWLEDGE)
NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK.
MASTER TO SLAVE
SLAVE TO MASTER
A
XXXXXXXX
XXXXXXXX
A
XXXXXXXX
A
XXXXXXXX
A
P
<DATA (n)> <DATA (n + 1)> <DATA (n + 2)> <DATA (n + X)>
...
DS3231
Extremely Accurate I
2
C-Integrated
RTC/TCXO/Crystal
www.maximintegrated.com
Maxim Integrated
│
17